📄 altsyncram_d4l1.tdf
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PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 23,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 14,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 23,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a38 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 23,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 15,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 23,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a39 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 16,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 23,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 16,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 23,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a40 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 17,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 23,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 17,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 23,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a41 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 23,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 18,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 23,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a42 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 23,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 19,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 23,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a43 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 23,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 20,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 23,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a44 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 23,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 21,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 23,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a45 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 23,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 22,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 23,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
address_a_wire[12..0] : WIRE;
address_b_wire[12..0] : WIRE;
BEGIN
address_reg_a[].CLK = clock0;
address_reg_a[].D = address_a[12..12];
address_reg_a[].ENA = clocken0;
address_reg_b[].CLK = clock1;
address_reg_b[].D = address_b[12..12];
address_reg_b[].ENA = clocken1;
decode3.data[0..0] = address_a_wire[12..12];
decode3.enable = wren_a;
decode4.data[0..0] = address_b_wire[12..12];
decode4.enable = wren_b;
decode_a.data[0..0] = address_a_wire[12..12];
decode_a.enable = clocken0;
decode_b.data[0..0] = address_b_wire[12..12];
decode_b.enable = clocken1;
mux5.data[] = ( ram_block2a[45..0].portadataout[0..0]);
mux5.sel[] = address_reg_a[].Q;
mux6.data[] = ( ram_block2a[45..0].portbdataout[0..0]);
mux6.sel[] = address_reg_b[].Q;
ram_block2a[45..0].clk0 = clock0;
ram_block2a[45..0].clk1 = clock1;
ram_block2a[45..0].ena0 = ( decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0]);
ram_block2a[45..0].ena1 = ( decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0]);
ram_block2a[45..0].portaaddr[] = ( address_a_wire[11..0]);
ram_block2a[0].portadatain[] = ( data_a[0..0]);
ram_block2a[1].portadatain[] = ( data_a[1..1]);
ram_block2a[2].portadatain[] = ( data_a[2..2]);
ram_block2a[3].portadatain[] = ( data_a[3..3]);
ram_block2a[4].portadatain[] = ( data_a[4..4]);
ram_block2a[5].portadatain[] = ( data_a[5..5]);
ram_block2a[6].portadatain[] = ( data_a[6..6]);
ram_block2a[7].portadatain[] = ( data_a[7..7]);
ram_block2a[8].portadatain[] = ( data_a[8..8]);
ram_block2a[9].portadatain[] = ( data_a[9..9]);
ram_block2a[10].portadatain[] = ( data_a[10..10]);
ram_block2a[11].portadatain[] = ( data_a[11..11]);
ram_block2a[12].portadatain[] = ( data_a[12..12]);
ram_block2a[13].portadatain[] = ( data_a[13..13]);
ram_block2a[14].portadatain[] = ( data_a[14..14]);
ram_block2a[15].portadatain[] = ( data_a[15..15]);
ram_block2a[16].portadatain[] = ( data_a[16..16]);
ram_block2a[17].portadatain[] = ( data_a[17..17]);
ram_block2a[18].portadatain[] = ( data_a[18..18]);
ram_block2a[19].portadatain[] = ( data_a[19..19]);
ram_block2a[20].portadatain[] = ( data_a[20..20]);
ram_block2a[21].portadatain[] = ( data_a[21..21]);
ram_block2a[22].portadatain[] = ( data_a[22..22]);
ram_block2a[23].portadatain[] = ( data_a[0..0]);
ram_block2a[24].portadatain[] = ( data_a[1..1]);
ram_block2a[25].portadatain[] = ( data_a[2..2]);
ram_block2a[26].portadatain[] = ( data_a[3..3]);
ram_block2a[27].portadatain[] = ( data_a[4..4]);
ram_block2a[28].portadatain[] = ( data_a[5..5]);
ram_block2a[29].portadatain[] = ( data_a[6..6]);
ram_block2a[30].portadatain[] = ( data_a[7..7]);
ram_block2a[31].portadatain[] = ( data_a[8..8]);
ram_block2a[32].portadatain[] = ( data_a[9..9]);
ram_block2a[33].portadatain[] = ( data_a[10..10]);
ram_block2a[34].portadatain[] = ( data_a[11..11]);
ram_block2a[35].portadatain[] = ( data_a[12..12]);
ram_block2a[36].portadatain[] = ( data_a[13..13]);
ram_block2a[37].portadatain[] = ( data_a[14..14]);
ram_block2a[38].portadatain[] = ( data_a[15..15]);
ram_block2a[39].portadatain[] = ( data_a[16..16]);
ram_block2a[40].portadatain[] = ( data_a[17..17]);
ram_block2a[41].portadatain[] = ( data_a[18..18]);
ram_block2a[42].portadatain[] = ( data_a[19..19]);
ram_block2a[43].portadatain[] = ( data_a[20..20]);
ram_block2a[44].portadatain[] = ( data_a[21..21]);
ram_block2a[45].portadatain[] = ( data_a[22..22]);
ram_block2a[45..0].portawe = ( decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);
ram_block2a[45..0].portbaddr[] = ( address_b_wire[11..0]);
ram_block2a[0].portbdatain[] = ( data_b[0..0]);
ram_block2a[1].portbdatain[] = ( data_b[1..1]);
ram_block2a[2].portbdatain[] = ( data_b[2..2]);
ram_block2a[3].portbdatain[] = ( data_b[3..3]);
ram_block2a[4].portbdatain[] = ( data_b[4..4]);
ram_block2a[5].portbdatain[] = ( data_b[5..5]);
ram_block2a[6].portbdatain[] = ( data_b[6..6]);
ram_block2a[7].portbdatain[] = ( data_b[7..7]);
ram_block2a[8].portbdatain[] = ( data_b[8..8]);
ram_block2a[9].portbdatain[] = ( data_b[9..9]);
ram_block2a[10].portbdatain[] = ( data_b[10..10]);
ram_block2a[11].portbdatain[] = ( data_b[11..11]);
ram_block2a[12].portbdatain[] = ( data_b[12..12]);
ram_block2a[13].portbdatain[] = ( data_b[13..13]);
ram_block2a[14].portbdatain[] = ( data_b[14..14]);
ram_block2a[15].portbdatain[] = ( data_b[15..15]);
ram_block2a[16].portbdatain[] = ( data_b[16..16]);
ram_block2a[17].portbdatain[] = ( data_b[17..17]);
ram_block2a[18].portbdatain[] = ( data_b[18..18]);
ram_block2a[19].portbdatain[] = ( data_b[19..19]);
ram_block2a[20].portbdatain[] = ( data_b[20..20]);
ram_block2a[21].portbdatain[] = ( data_b[21..21]);
ram_block2a[22].portbdatain[] = ( data_b[22..22]);
ram_block2a[23].portbdatain[] = ( data_b[0..0]);
ram_block2a[24].portbdatain[] = ( data_b[1..1]);
ram_block2a[25].portbdatain[] = ( data_b[2..2]);
ram_block2a[26].portbdatain[] = ( data_b[3..3]);
ram_block2a[27].portbdatain[] = ( data_b[4..4]);
ram_block2a[28].portbdatain[] = ( data_b[5..5]);
ram_block2a[29].portbdatain[] = ( data_b[6..6]);
ram_block2a[30].portbdatain[] = ( data_b[7..7]);
ram_block2a[31].portbdatain[] = ( data_b[8..8]);
ram_block2a[32].portbdatain[] = ( data_b[9..9]);
ram_block2a[33].portbdatain[] = ( data_b[10..10]);
ram_block2a[34].portbdatain[] = ( data_b[11..11]);
ram_block2a[35].portbdatain[] = ( data_b[12..12]);
ram_block2a[36].portbdatain[] = ( data_b[13..13]);
ram_block2a[37].portbdatain[] = ( data_b[14..14]);
ram_block2a[38].portbdatain[] = ( data_b[15..15]);
ram_block2a[39].portbdatain[] = ( data_b[16..16]);
ram_block2a[40].portbdatain[] = ( data_b[17..17]);
ram_block2a[41].portbdatain[] = ( data_b[18..18]);
ram_block2a[42].portbdatain[] = ( data_b[19..19]);
ram_block2a[43].portbdatain[] = ( data_b[20..20]);
ram_block2a[44].portbdatain[] = ( data_b[21..21]);
ram_block2a[45].portbdatain[] = ( data_b[22..22]);
ram_block2a[45..0].portbrewe = ( decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0]);
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_a[] = mux5.result[];
q_b[] = mux6.result[];
END;
--VALID FILE
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