📄 altsyncram_p4l1.tdf
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PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 17,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a46 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 18,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 28,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 18,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a47 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 19,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 28,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 19,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a48 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 20,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 28,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 20,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a49 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 21,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 28,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 21,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a50 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 22,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 28,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 22,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a51 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 23,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 28,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 23,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a52 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 28,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 24,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a53 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 25,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 28,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 25,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a54 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 28,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 26,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block2a55 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 28,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 27,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 28,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
address_a_wire[12..0] : WIRE;
address_b_wire[12..0] : WIRE;
BEGIN
address_reg_a[].CLK = clock0;
address_reg_a[].D = address_a[12..12];
address_reg_a[].ENA = clocken0;
address_reg_b[].CLK = clock1;
address_reg_b[].D = address_b[12..12];
address_reg_b[].ENA = clocken1;
decode3.data[0..0] = address_a_wire[12..12];
decode3.enable = wren_a;
decode4.data[0..0] = address_b_wire[12..12];
decode4.enable = wren_b;
decode_a.data[0..0] = address_a_wire[12..12];
decode_a.enable = clocken0;
decode_b.data[0..0] = address_b_wire[12..12];
decode_b.enable = clocken1;
mux5.data[] = ( ram_block2a[55..0].portadataout[0..0]);
mux5.sel[] = address_reg_a[].Q;
mux6.data[] = ( ram_block2a[55..0].portbdataout[0..0]);
mux6.sel[] = address_reg_b[].Q;
ram_block2a[55..0].clk0 = clock0;
ram_block2a[55..0].clk1 = clock1;
ram_block2a[55..0].ena0 = ( decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0]);
ram_block2a[55..0].ena1 = ( decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0]);
ram_block2a[55..0].portaaddr[] = ( address_a_wire[11..0]);
ram_block2a[0].portadatain[] = ( data_a[0..0]);
ram_block2a[1].portadatain[] = ( data_a[1..1]);
ram_block2a[2].portadatain[] = ( data_a[2..2]);
ram_block2a[3].portadatain[] = ( data_a[3..3]);
ram_block2a[4].portadatain[] = ( data_a[4..4]);
ram_block2a[5].portadatain[] = ( data_a[5..5]);
ram_block2a[6].portadatain[] = ( data_a[6..6]);
ram_block2a[7].portadatain[] = ( data_a[7..7]);
ram_block2a[8].portadatain[] = ( data_a[8..8]);
ram_block2a[9].portadatain[] = ( data_a[9..9]);
ram_block2a[10].portadatain[] = ( data_a[10..10]);
ram_block2a[11].portadatain[] = ( data_a[11..11]);
ram_block2a[12].portadatain[] = ( data_a[12..12]);
ram_block2a[13].portadatain[] = ( data_a[13..13]);
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