altsyncram_25l1.tdf

用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开发板

			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 10,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a11 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 4095,
			PORT_A_LOGICAL_RAM_DEPTH = 4096,
			PORT_A_LOGICAL_RAM_WIDTH = 21,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 11,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a12 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 4095,
			PORT_A_LOGICAL_RAM_DEPTH = 4096,
			PORT_A_LOGICAL_RAM_WIDTH = 21,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 12,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a13 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 4095,
			PORT_A_LOGICAL_RAM_DEPTH = 4096,
			PORT_A_LOGICAL_RAM_WIDTH = 21,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 13,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a14 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 4095,
			PORT_A_LOGICAL_RAM_DEPTH = 4096,
			PORT_A_LOGICAL_RAM_WIDTH = 21,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 14,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a15 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 4095,
			PORT_A_LOGICAL_RAM_DEPTH = 4096,
			PORT_A_LOGICAL_RAM_WIDTH = 21,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 15,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a16 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 4095,
			PORT_A_LOGICAL_RAM_DEPTH = 4096,
			PORT_A_LOGICAL_RAM_WIDTH = 21,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 16,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a17 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 4095,
			PORT_A_LOGICAL_RAM_DEPTH = 4096,
			PORT_A_LOGICAL_RAM_WIDTH = 21,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 17,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a18 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 4095,
			PORT_A_LOGICAL_RAM_DEPTH = 4096,
			PORT_A_LOGICAL_RAM_WIDTH = 21,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 18,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a19 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 4095,
			PORT_A_LOGICAL_RAM_DEPTH = 4096,
			PORT_A_LOGICAL_RAM_WIDTH = 21,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 19,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block2a20 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 4095,
			PORT_A_LOGICAL_RAM_DEPTH = 4096,
			PORT_A_LOGICAL_RAM_WIDTH = 21,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 20,
			PORT_B_LAST_ADDRESS = 4095,
			PORT_B_LOGICAL_RAM_DEPTH = 4096,
			PORT_B_LOGICAL_RAM_WIDTH = 21,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[11..0]	: WIRE;
	address_b_wire[11..0]	: WIRE;

BEGIN 
	ram_block2a[20..0].clk0 = clock0;
	ram_block2a[20..0].clk1 = clock1;
	ram_block2a[20..0].ena0 = clocken0;
	ram_block2a[20..0].ena1 = clocken1;
	ram_block2a[20..0].portaaddr[] = ( address_a_wire[11..0]);
	ram_block2a[0].portadatain[] = ( data_a[0..0]);
	ram_block2a[1].portadatain[] = ( data_a[1..1]);
	ram_block2a[2].portadatain[] = ( data_a[2..2]);
	ram_block2a[3].portadatain[] = ( data_a[3..3]);
	ram_block2a[4].portadatain[] = ( data_a[4..4]);
	ram_block2a[5].portadatain[] = ( data_a[5..5]);
	ram_block2a[6].portadatain[] = ( data_a[6..6]);
	ram_block2a[7].portadatain[] = ( data_a[7..7]);
	ram_block2a[8].portadatain[] = ( data_a[8..8]);
	ram_block2a[9].portadatain[] = ( data_a[9..9]);
	ram_block2a[10].portadatain[] = ( data_a[10..10]);
	ram_block2a[11].portadatain[] = ( data_a[11..11]);
	ram_block2a[12].portadatain[] = ( data_a[12..12]);
	ram_block2a[13].portadatain[] = ( data_a[13..13]);
	ram_block2a[14].portadatain[] = ( data_a[14..14]);
	ram_block2a[15].portadatain[] = ( data_a[15..15]);
	ram_block2a[16].portadatain[] = ( data_a[16..16]);
	ram_block2a[17].portadatain[] = ( data_a[17..17]);
	ram_block2a[18].portadatain[] = ( data_a[18..18]);
	ram_block2a[19].portadatain[] = ( data_a[19..19]);
	ram_block2a[20].portadatain[] = ( data_a[20..20]);
	ram_block2a[20..0].portawe = wren_a;
	ram_block2a[20..0].portbaddr[] = ( address_b_wire[11..0]);
	ram_block2a[0].portbdatain[] = ( data_b[0..0]);
	ram_block2a[1].portbdatain[] = ( data_b[1..1]);
	ram_block2a[2].portbdatain[] = ( data_b[2..2]);
	ram_block2a[3].portbdatain[] = ( data_b[3..3]);
	ram_block2a[4].portbdatain[] = ( data_b[4..4]);
	ram_block2a[5].portbdatain[] = ( data_b[5..5]);
	ram_block2a[6].portbdatain[] = ( data_b[6..6]);
	ram_block2a[7].portbdatain[] = ( data_b[7..7]);
	ram_block2a[8].portbdatain[] = ( data_b[8..8]);
	ram_block2a[9].portbdatain[] = ( data_b[9..9]);
	ram_block2a[10].portbdatain[] = ( data_b[10..10]);
	ram_block2a[11].portbdatain[] = ( data_b[11..11]);
	ram_block2a[12].portbdatain[] = ( data_b[12..12]);
	ram_block2a[13].portbdatain[] = ( data_b[13..13]);
	ram_block2a[14].portbdatain[] = ( data_b[14..14]);
	ram_block2a[15].portbdatain[] = ( data_b[15..15]);
	ram_block2a[16].portbdatain[] = ( data_b[16..16]);
	ram_block2a[17].portbdatain[] = ( data_b[17..17]);
	ram_block2a[18].portbdatain[] = ( data_b[18..18]);
	ram_block2a[19].portbdatain[] = ( data_b[19..19]);
	ram_block2a[20].portbdatain[] = ( data_b[20..20]);
	ram_block2a[20..0].portbrewe = wren_b;
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_a[] = ( ram_block2a[20..0].portadataout[0..0]);
	q_b[] = ( ram_block2a[20..0].portbdataout[0..0]);
END;
--VALID FILE