am_adjust.vhd

来自「用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity am_adjust is
port(keyclk,key:in std_logic; 
     am_adj_coefi:out std_logic_vector(4 downto 0));
end am_adjust;

architecture rtl of am_adjust is
signal datb:integer range 0 to 10;
signal key0,key1,key_en:std_logic;

begin

process(keyclk)
begin
    if(keyclk'event and keyclk='0')then
       key1<=key0;
	   key0<=key;
    end if;
end process;

process(key0,key1)
begin
    key_en<=keyclk and key0 and (not key1);
end process;

process(key_en)
begin
    if(key_en'event and key_en='1')then
         if(datb=10)then
            datb<=0;
          else 
            datb<=datb+1;
          end if;
   end if;
am_adj_coefi<=conv_std_logic_vector(datb,5);
end process;

end rtl;