sin_gen.map.rpt

用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开发板

 75. Parameter Settings for User Entity Instance: fm_modulate:inst3|lpm_rom_fm:inst1|altsyncram:altsyncram_component
 76. Parameter Settings for User Entity Instance: mux_2_4:inst6|LPM_MUX:lpm_mux_component
 77. Parameter Settings for User Entity Instance: lpm_multi1:inst15|lpm_mult:lpm_mult_component
 78. Parameter Settings for User Entity Instance: am_modulate:inst18|lpm_add0:inst14|lpm_add_sub:lpm_add_sub_component
 79. Parameter Settings for User Entity Instance: am_modulate:inst18|lpm_multi0:inst16|lpm_mult:lpm_mult_component
 80. Parameter Settings for User Entity Instance: am_modulate:inst18|lpm_sub0:inst15|lpm_add_sub:lpm_add_sub_component
 81. Parameter Settings for User Entity Instance: am_modulate:inst18|lpm_rom0:inst12|altsyncram:altsyncram_component
 82. Parameter Settings for User Entity Instance: a_psk:inst10|lpm_sub128:inst5|lpm_add_sub:lpm_add_sub_component
 83. Parameter Settings for User Entity Instance: a_psk:inst10|lpm_rom_apsk:inst|altsyncram:altsyncram_component
 84. Parameter Settings for Inferred Entity Instance: pzdyqx:nabboc
 85. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 86. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 87. lpm_mult Parameter Settings by Entity Instance
 88. SignalTap II Logic Analyzer Settings
 89. Analysis & Synthesis Messages



----------------
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without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
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+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri Sep 21 22:25:55 2007    ;
; Quartus II Version                 ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name                      ; sin_gen                                  ;
; Top-level Entity Name              ; sin_gen                                  ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 796                                      ;
; Total registers                    ; 664                                      ;
; Total pins                         ; 26                                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 75,776                                   ;
; Embedded Multiplier 9-bit elements ; 10                                       ;
; Total PLLs                         ; 1                                        ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C6       ;                    ;
; Top-level entity name                                              ; sin_gen            ; sin_gen            ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; On                 ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;