key_delay.vhd

来自「用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity key_delay is
port(keyclk,key100,key100k:in std_logic;
     key_en100,key_en100k:out std_logic);
end key_delay;

architecture rtl of key_delay is
signal key0,key1,key_0,key_1:std_logic;
begin

process(keyclk)
begin
    if(keyclk'event and keyclk='0')then
       key1<=key0;
	   key0<=key100;
	   key_1<=key_0;
	   key_0<=key100k;
    end if;
end process;

process(key0,key1,key_0,key_1)
begin
    key_en100<=keyclk and key0 and (not key1);
    key_en100k<=keyclk and key_0 and (not key_1);
end process;

end rtl;