cnt99.vhd

来自「用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity cnt99 is
port(clk1M:in std_logic;
     add_out:out std_logic_vector(6 downto 0));
end cnt99;

architecture rtl of cnt99 is
signal data:integer range 0 to 98;
begin

process(clk1M)
begin
    if(clk1M'event and clk1M='1')then
        if(data=98)then
           data<=0;
        else 
           data<=data+1;
        end if;
   end if;
add_out<=conv_std_logic_vector(data,7);
end process;
end rtl;