📄 cnt99.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cnt99 is
port(clk1M:in std_logic;
add_out:out std_logic_vector(6 downto 0));
end cnt99;
architecture rtl of cnt99 is
signal data:integer range 0 to 98;
begin
process(clk1M)
begin
if(clk1M'event and clk1M='1')then
if(data=98)then
data<=0;
else
data<=data+1;
end if;
end if;
add_out<=conv_std_logic_vector(data,7);
end process;
end rtl;
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