div40.vhd

来自「用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity div40 is
port(clk1k:in std_logic;
     keyclk:out std_logic);
end div40;

architecture rtl of div40 is
signal data:integer range 0 to 39;
--signal q:std_logic;
begin

process(clk1k)
begin
    if(clk1k'event and clk1k='1')then
        if(data=39)then
           data<=0;
     	   keyclk<='1';
        else 
           data<=data+1;
           keyclk<='0';
        end if;
   end if;

end process;
end rtl;