📄 cnt1000.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cnt1000 is
port(clk1M:in std_logic;
add_out:out std_logic_vector(9 downto 0));
end cnt1000;
architecture rtl of cnt1000 is
signal data:integer range 0 to 999;
begin
process(clk1M)
begin
if(clk1M'event and clk1M='1')then
if(data=999)then
data<=0;
else
data<=data+1;
end if;
end if;
add_out<=conv_std_logic_vector(data,10);
end process;
end rtl;
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