📄 f_word_gen.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity key_delay is
port(clk,reset:in std_logic;
fre_word:out std_logic_vector(31 downto 0));
end key_delay;
architecture rtl of key_delay is
begin
process(keyclk)
begin
if(keyclk'event and keyclk='0')then
key1<=key0;
key0<=key;
end if;
end process;
process(key0,key1)
begin
key_en<=keyclk and key0 and (not key1);
end process;
end rtl;
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