📄 m_signal.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity m_signal is
port(clk10k:in std_logic;
q:out std_logic);
end m_signal;
architecture behav of m_signal is
signal data:integer range 0 to 6;
begin
process(clk10k)
begin
if(clk10k'event and clk10k='1')then
if(data=6)then
data<=0;
else
data<=data+1;
end if;
end if;
end process;
process(data)
begin
if(clk10k'event and clk10k='1')then
if(data=0)then
q<='0';
elsif(data=1)then
q<='1';
elsif(data=2)then
q<='0';
elsif(data=3)then
q<='0';
elsif(data=4)then
q<='1';
elsif(data=5)then
q<='1';
else
q<='1';
end if;
end if;
end process;
end behav;
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