padd0.vhd

来自「用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开」· VHDL 代码 · 共 16 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;

entity padd0 is
port(datain:in std_logic_vector(19 downto 0);
     dataout:out std_logic_vector(31 downto 0));
end padd0;

architecture rtl of padd0 is
--signal s_fre_word:integer range 0 to 2**32;
begin
  dataout<="000000000000"&datain;
end rtl;