sin_gen.tan.summary

用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开发板

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.020 ns
From           : sw1
To             : NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_altqmcpipe:ux000|phi_int_arr_reg[10]
From Clock     : --
To Clock       : clk50m
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 31.828 ns
From           : am_modulate:inst18|am_adjust:inst10|datb[3]
To             : q_out[6]
From Clock     : clk50m
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 8.847 ns
From           : sw1
To             : q_out[6]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 9.913 ns
From           : am_adj
To             : am_modulate:inst18|am_adjust:inst10|key0
From Clock     : --
To Clock       : clk50m
Failed Paths   : 0

Type           : Clock Setup: 'pll:inst1|altpll:altpll_component|_clk0'
Slack          : -18.340 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 35.29 MHz ( period = 28.340 ns )
From           : fre_word_gen:inst13|cnt99:inst24|data[0]
To             : NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_altqmcpipe:ux000|phi_int_arr_reg[31]
From Clock     : pll:inst1|altpll:altpll_component|_clk0
To Clock       : pll:inst1|altpll:altpll_component|_clk0
Failed Paths   : 704

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 127.45 MHz ( period = 7.846 ns )
From           : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~CLKDRUSER'
Slack          : N/A
Required Time  : None
Actual Time    : 370.64 MHz ( period = 2.698 ns )
From           : pzdyqx:nabboc|VELJ8121:JDCF0099|AJQN5180[1]
To             : pzdyqx:nabboc|VELJ8121:JDCF0099|DJFL8584[1]
From Clock     : altera_internal_jtag~CLKDRUSER
To Clock       : altera_internal_jtag~CLKDRUSER
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~UPDATEUSER'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : pzdyqx:nabboc|XWDE0671[2]
To             : pzdyqx:nabboc|XWDE0671[1]
From Clock     : altera_internal_jtag~UPDATEUSER
To Clock       : altera_internal_jtag~UPDATEUSER
Failed Paths   : 0

Type           : Clock Hold: 'pll:inst1|altpll:altpll_component|_clk0'
Slack          : -4.195 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component|add_sub_0ck:auto_generated|pipeline_dffe[6]~_Duplicate_1
To             : sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[6]
From Clock     : pll:inst1|altpll:altpll_component|_clk0
To Clock       : pll:inst1|altpll:altpll_component|_clk0
Failed Paths   : 314

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1018

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