const1m.vhd

来自「用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity const1M is
port(clk100M:in std_logic;
     const_1M:out std_logic_vector(31 downto 0));
end const1M;

architecture rtl of const1M is
begin

process(clk100M)
begin
    if(clk100M'event and clk100M='1')then
       const_1M<=X"028F5C29";
	 end if;
end process;
end rtl;