📄 cnt100.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cnt100 is
port(clk100M:in std_logic;
clk1M:out std_logic);
end cnt100;
architecture rtl of cnt100 is
signal data:integer range 0 to 99;
--signal q:std_logic;
begin
process(clk100M)
begin
if(clk100M'event and clk100M='1')then
if(data=99)then
data<=0;
clk1M<='1';
else
data<=data+1;
clk1M<='0';
end if;
end if;
end process;
end rtl;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -