sin_gen.tan.rpt

用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开发板

; Type                                                   ; Slack      ; Required Time                     ; Actual Time                                    ; From                                                                                                                                                  ; To                                                                               ; From Clock                              ; To Clock                                ; Failed Paths ;
+--------------------------------------------------------+------------+-----------------------------------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Worst-case tsu                                         ; N/A        ; None                              ; 4.020 ns                                       ; sw1                                                                                                                                                   ; NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_altqmcpipe:ux000|phi_int_arr_reg[10] ; --                                      ; clk50m                                  ; 0            ;
; Worst-case tco                                         ; N/A        ; None                              ; 31.828 ns                                      ; am_modulate:inst18|am_adjust:inst10|datb[3]                                                                                                           ; q_out[6]                                                                         ; clk50m                                  ; --                                      ; 0            ;
; Worst-case tpd                                         ; N/A        ; None                              ; 8.847 ns                                       ; sw1                                                                                                                                                   ; q_out[6]                                                                         ; --                                      ; --                                      ; 0            ;
; Worst-case th                                          ; N/A        ; None                              ; 9.913 ns                                       ; am_adj                                                                                                                                                ; am_modulate:inst18|am_adjust:inst10|key0                                         ; --                                      ; clk50m                                  ; 0            ;
; Clock Setup: 'pll:inst1|altpll:altpll_component|_clk0' ; -18.340 ns ; 100.00 MHz ( period = 10.000 ns ) ; 35.29 MHz ( period = 28.340 ns )               ; fre_word_gen:inst13|cnt99:inst24|data[0]                                                                                                              ; NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_altqmcpipe:ux000|phi_int_arr_reg[31] ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 704          ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'            ; N/A        ; None                              ; 127.45 MHz ( period = 7.846 ns )               ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]                                                                               ; sld_hub:sld_hub_inst|hub_tdo                                                     ; altera_internal_jtag~TCKUTAP            ; altera_internal_jtag~TCKUTAP            ; 0            ;
; Clock Setup: 'altera_internal_jtag~CLKDRUSER'          ; N/A        ; None                              ; 370.64 MHz ( period = 2.698 ns )               ; pzdyqx:nabboc|VELJ8121:JDCF0099|AJQN5180[1]                                                                                                           ; pzdyqx:nabboc|VELJ8121:JDCF0099|DJFL8584[1]                                      ; altera_internal_jtag~CLKDRUSER          ; altera_internal_jtag~CLKDRUSER          ; 0            ;
; Clock Setup: 'altera_internal_jtag~UPDATEUSER'         ; N/A        ; None                              ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; pzdyqx:nabboc|XWDE0671[2]                                                                                                                             ; pzdyqx:nabboc|XWDE0671[1]                                                        ; altera_internal_jtag~UPDATEUSER         ; altera_internal_jtag~UPDATEUSER         ; 0            ;
; Clock Hold: 'pll:inst1|altpll:altpll_component|_clk0'  ; -4.195 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                                            ; NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_nco_mob_w:blk0|lpm_add_sub:lpm_add_sub_component|add_sub_0ck:auto_generated|pipeline_dffe[6]~_Duplicate_1 ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[6]                             ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 314          ;
; Total number of failed paths                           ;            ;                                   ;                                                ;                                                                                                                                                       ;                                                                                  ;                                         ;                                         ; 1018         ;
+--------------------------------------------------------+------------+-----------------------------------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+-------------------------------------------------------+--------------------+------+------------------+-------------+
; Option                                                ; Setting            ; From ; To               ; Entity Name ;
+-------------------------------------------------------+--------------------+------+------------------+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;                  ;             ;
; Timing Models                                         ; Final              ;      ;                  ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;                  ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;                  ;             ;
; Number of paths to report                             ; 200                ;      ;                  ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;                  ;             ;
; Use Fast Timing Models                                ; Off                ;      ;                  ;             ;
; Report IO Paths Separately                            ; Off                ;      ;                  ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;                  ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;                  ;             ;
; Cut off read during write signal paths                ; On                 ;      ;                  ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;                  ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;                  ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;                  ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;                  ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;                  ;             ;
; Enable Clock Latency                                  ; Off                ;      ;                  ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;                  ;             ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_0       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_1       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_2       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_3       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_4       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_5       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_6       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; EPEO2888_7       ; MDCK2395    ;
; Cut Timing Path                                       ; On                 ;      ; lcell:LJMV0916_0 ; MDCK2395    ;