📄 ask_m.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ask_m is
port(q:in std_logic;
ask_in:in std_logic_vector(7 downto 0);
ask_out:out std_logic_vector(7 downto 0));
end ask_m;
architecture behav of ask_m is
begin
process(q)
begin
if(q='1')then
ask_out<=ask_in;
else
ask_out<="00000000";
end if;
end process;
end behav;
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