unsigned_4_adder.vhd

通过vhdl语言实现四位无符号数的加法

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity unsigned_4_adder is
	port(a,b:in std_logic_vector(3 downto 0);
		y:out std_logic;
		Dout:out std_logic_vector(7 downto 0);
		Sel:out std_logic);
end unsigned_4_adder;

architecture add of unsigned_4_adder is
	signal total:std_logic_vector(3 downto 0);
	begin
	total<=a+b;
		process(total)
		begin
			if(total<a or total<b) then y<='1';
			else y<='0';
			end if;
			
			Sel<='0';
			
			case total is
				when "0000" =>Dout<="00111111"; --0
				when "0001" =>Dout<="00000110"; --1
				when "0010" =>Dout<="01011011"; --2
				when "0011" =>Dout<="01001111"; --3
				when "0100" =>Dout<="01100110"; --4
				when "0101" =>Dout<="01101101"; --5
				when "0110" =>Dout<="01111101"; --6
				when "0111" =>Dout<="00000111"; --7
				when "1000" =>Dout<="01111111"; --8
				when "1001" =>Dout<="01101111"; --9
				when "1010" =>Dout<="01110111"; --a
				when "1011" =>Dout<="01111100"; --b
				when "1100" =>Dout<="00111001"; --c
				when "1101" =>Dout<="01011110"; --d
				when "1110" =>Dout<="01111001"; --e
				when "1111" =>Dout<="01110001"; --f
			end case;
		end process;
end add;