ctr.tan.rpt

用cpld控制时序通过usb传送数据到pc机的vhdl源码

; N/A           ; None        ; -1.100 ns ; pa_in[0] ; counter16[2] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[0] ; counter16[1] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[0] ; counter16[4] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[0] ; counter16[5] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[0] ; addr[0]~reg0 ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[0] ; r_c~reg0     ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[0] ; addr[1]~reg0 ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[0] ; addr[3]~reg0 ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[0] ; addr[2]~reg0 ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; led1~reg0    ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter64[0] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter64[7] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter64[6] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter64[5] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter64[4] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter64[3] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter64[2] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter64[1] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter16[0] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter16[3] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter16[2] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter16[1] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter16[4] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; counter16[5] ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; addr[0]~reg0 ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; r_c~reg0     ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; addr[1]~reg0 ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; addr[3]~reg0 ; clk      ;
; N/A           ; None        ; -1.100 ns ; pa_in[1] ; addr[2]~reg0 ; clk      ;
+---------------+-------------+-----------+----------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Dec 01 14:22:51 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ctr -c ctr
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 153.85 MHz between source register "counter64[0]" and destination register "addr[0]~reg0" (period= 6.5 ns)
    Info: + Longest register to register delay is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC30; Fanout = 44; REG Node = 'counter64[0]'
        Info: 2: + IC(1.200 ns) + CELL(1.800 ns) = 3.000 ns; Loc. = SEXP62; Fanout = 2; COMB Node = 'addr~3325'
        Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 4.500 ns; Loc. = LC49; Fanout = 2; REG Node = 'addr[0]~reg0'
        Info: Total cell delay = 3.300 ns ( 73.33 % )
        Info: Total interconnect delay = 1.200 ns ( 26.67 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.600 ns
            Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_37; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC49; Fanout = 2; REG Node = 'addr[0]~reg0'
            Info: Total cell delay = 1.600 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 1.600 ns
            Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_37; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC30; Fanout = 44; REG Node = 'counter64[0]'
            Info: Total cell delay = 1.600 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Micro setup delay of destination is 1.300 ns
Info: tsu for register "addr[3]~reg0" (data pin = "pa3", clock pin = "clk") is 3.400 ns
    Info: + Longest pin to register delay is 3.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.600 ns) = 0.600 ns; Loc. = PIN_8; Fanout = 53; PIN Node = 'pa3'
        Info: 2: + IC(1.200 ns) + CELL(0.600 ns) = 2.400 ns; Loc. = LC45; Fanout = 1; COMB Node = 'addr[1]~3361'
        Info: 3: + IC(0.000 ns) + CELL(1.300 ns) = 3.700 ns; Loc. = LC46; Fanout = 13; REG Node = 'addr[3]~reg0'
        Info: Total cell delay = 2.500 ns ( 67.57 % )
        Info: Total interconnect delay = 1.200 ns ( 32.43 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock "clk" to destination register is 1.600 ns
        Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_37; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC46; Fanout = 13; REG Node = 'addr[3]~reg0'
        Info: Total cell delay = 1.600 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "slwr" through register "fiford~reg0" is 6.200 ns
    Info: + Longest clock path from clock "clk" to source register is 1.600 ns
        Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_37; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC20; Fanout = 2; REG Node = 'fiford~reg0'
        Info: Total cell delay = 1.600 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Longest register to pin delay is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC20; Fanout = 2; REG Node = 'fiford~reg0'
        Info: 2: + IC(1.000 ns) + CELL(2.100 ns) = 3.100 ns; Loc. = LC62; Fanout = 1; COMB Node = 'fiford~14'
        Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 3.900 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'slwr'
        Info: Total cell delay = 2.900 ns ( 74.36 % )
        Info: Total interconnect delay = 1.000 ns ( 25.64 % )
Info: Longest tpd from source pin "pa_in[1]" to destination pin "ctr" is 4.700 ns
    Info: 1: + IC(0.000 ns) + CELL(0.600 ns) = 0.600 ns; Loc. = PIN_5; Fanout = 53; PIN Node = 'pa_in[1]'
    Info: 2: + IC(1.200 ns) + CELL(2.100 ns) = 3.900 ns; Loc. = LC52; Fanout = 1; COMB Node = 'Equal0~15'
    Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 4.700 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'ctr'
    Info: Total cell delay = 3.500 ns ( 74.47 % )
    Info: Total interconnect delay = 1.200 ns ( 25.53 % )
Info: th for register "q[0]" (data pin = "Uflag[1]", clock pin = "clk") is 0.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 1.600 ns
        Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_37; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC27; Fanout = 2; REG Node = 'q[0]'
        Info: Total cell delay = 1.600 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 0.600 ns
    Info: - Shortest pin to register delay is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.600 ns) = 0.600 ns; Loc. = PIN_44; Fanout = 2; PIN Node = 'Uflag[1]'
        Info: 2: + IC(1.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC27; Fanout = 2; REG Node = 'q[0]'
        Info: Total cell delay = 1.200 ns ( 54.55 % )
        Info: Total interconnect delay = 1.000 ns ( 45.45 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Dec 01 14:22:52 2006
    Info: Elapsed time: 00:00:01