ctr.qsf

用cpld控制时序通过usb传送数据到pc机的vhdl源码

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		ctr_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:28:13  MARCH 24, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name SOURCE_FILE unity
set_global_assignment -name VHDL_FILE ctr.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_43 -to Uflag[0]
set_location_assignment PIN_44 -to Uflag[1]
set_location_assignment PIN_2 -to Uflag[2]
set_location_assignment PIN_27 -to addr[0]
set_location_assignment PIN_28 -to addr[1]
set_location_assignment PIN_33 -to addr[2]
set_location_assignment PIN_25 -to addr[3]
set_location_assignment PIN_23 -to busy
set_location_assignment PIN_37 -to clk
set_location_assignment PIN_30 -to ctr
set_location_assignment PIN_19 -to empty
set_location_assignment PIN_13 -to fiford
set_location_assignment PIN_14 -to fifowr
set_location_assignment PIN_42 -to ifclk
set_location_assignment PIN_21 -to led1
set_location_assignment PIN_22 -to led2
set_location_assignment PIN_6 -to pa2
set_location_assignment PIN_8 -to pa3
set_location_assignment PIN_10 -to pa4
set_location_assignment PIN_11 -to pa5
set_location_assignment PIN_12 -to pa6
set_location_assignment PIN_15 -to pa7
set_location_assignment PIN_3 -to pa_in[0]
set_location_assignment PIN_5 -to pa_in[1]
set_location_assignment PIN_31 -to r_c
set_location_assignment PIN_18 -to reset
set_location_assignment PIN_35 -to slrd
set_location_assignment PIN_34 -to slwr
set_location_assignment PIN_20 -to rstfifo

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
set_global_assignment -name FAMILY MAX7000AE
set_global_assignment -name TOP_LEVEL_ENTITY ctr

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM7064AETC44-4"

set_global_assignment -name VHDL_FILE "ctr 1101.vhd"