ctr.tan.qmsg

用cpld控制时序通过usb传送数据到pc机的vhdl源码

{ "Info" "ITDB_TSU_RESULT" "addr\[3\]~reg0 pa3 clk 3.400 ns register " "Info: tsu for register \"addr\[3\]~reg0\" (data pin = \"pa3\", clock pin = \"clk\") is 3.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Longest pin register " "Info: + Longest pin to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 0.600 ns pa3 1 PIN PIN_8 53 " "Info: 1: + IC(0.000 ns) + CELL(0.600 ns) = 0.600 ns; Loc. = PIN_8; Fanout = 53; PIN Node = 'pa3'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pa3 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.600 ns) 2.400 ns addr\[1\]~3361 2 COMB LC45 1 " "Info: 2: + IC(1.200 ns) + CELL(0.600 ns) = 2.400 ns; Loc. = LC45; Fanout = 1; COMB Node = 'addr\[1\]~3361'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { pa3 addr[1]~3361 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.700 ns addr\[3\]~reg0 3 REG LC46 13 " "Info: 3: + IC(0.000 ns) + CELL(1.300 ns) = 3.700 ns; Loc. = LC46; Fanout = 13; REG Node = 'addr\[3\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { addr[1]~3361 addr[3]~reg0 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 67.57 % ) " "Info: Total cell delay = 2.500 ns ( 67.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 32.43 % ) " "Info: Total interconnect delay = 1.200 ns ( 32.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.700 ns" { pa3 addr[1]~3361 addr[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.700 ns" { pa3 pa3~out addr[1]~3361 addr[3]~reg0 } { 0.000ns 0.000ns 1.200ns 0.000ns } { 0.000ns 0.600ns 0.600ns 1.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 89 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.600 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns clk 1 CLK PIN_37 22 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_37; Fanout = 22; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.600 ns addr\[3\]~reg0 2 REG LC46 13 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC46; Fanout = 13; REG Node = 'addr\[3\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { clk addr[3]~reg0 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { clk addr[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.600 ns" { clk clk~out addr[3]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.700 ns" { pa3 addr[1]~3361 addr[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.700 ns" { pa3 pa3~out addr[1]~3361 addr[3]~reg0 } { 0.000ns 0.000ns 1.200ns 0.000ns } { 0.000ns 0.600ns 0.600ns 1.300ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { clk addr[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.600 ns" { clk clk~out addr[3]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk slwr fiford~reg0 6.200 ns register " "Info: tco from clock \"clk\" to destination pin \"slwr\" through register \"fiford~reg0\" is 6.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns clk 1 CLK PIN_37 22 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_37; Fanout = 22; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.600 ns fiford~reg0 2 REG LC20 2 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC20; Fanout = 2; REG Node = 'fiford~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { clk fiford~reg0 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { clk fiford~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.600 ns" { clk clk~out fiford~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 152 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns + Longest register pin " "Info: + Longest register to pin delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fiford~reg0 1 REG LC20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC20; Fanout = 2; REG Node = 'fiford~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fiford~reg0 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.100 ns) 3.100 ns fiford~14 2 COMB LC62 1 " "Info: 2: + IC(1.000 ns) + CELL(2.100 ns) = 3.100 ns; Loc. = LC62; Fanout = 1; COMB Node = 'fiford~14'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { fiford~reg0 fiford~14 } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.900 ns slwr 3 PIN PIN_34 0 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 3.900 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'slwr'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { fiford~14 slwr } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 74.36 % ) " "Info: Total cell delay = 2.900 ns ( 74.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 25.64 % ) " "Info: Total interconnect delay = 1.000 ns ( 25.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { fiford~reg0 fiford~14 slwr } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { fiford~reg0 fiford~14 slwr } { 0.000ns 1.000ns 0.000ns } { 0.000ns 2.100ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { clk fiford~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.600 ns" { clk clk~out fiford~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { fiford~reg0 fiford~14 slwr } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { fiford~reg0 fiford~14 slwr } { 0.000ns 1.000ns 0.000ns } { 0.000ns 2.100ns 0.800ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "pa_in\[1\] ctr 4.700 ns Longest " "Info: Longest tpd from source pin \"pa_in\[1\]\" to destination pin \"ctr\" is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 0.600 ns pa_in\[1\] 1 PIN PIN_5 53 " "Info: 1: + IC(0.000 ns) + CELL(0.600 ns) = 0.600 ns; Loc. = PIN_5; Fanout = 53; PIN Node = 'pa_in\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pa_in[1] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.100 ns) 3.900 ns Equal0~15 2 COMB LC52 1 " "Info: 2: + IC(1.200 ns) + CELL(2.100 ns) = 3.900 ns; Loc. = LC52; Fanout = 1; COMB Node = 'Equal0~15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.300 ns" { pa_in[1] Equal0~15 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 4.700 ns ctr 3 PIN PIN_30 0 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 4.700 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'ctr'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { Equal0~15 ctr } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 74.47 % ) " "Info: Total cell delay = 3.500 ns ( 74.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 25.53 % ) " "Info: Total interconnect delay = 1.200 ns ( 25.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.700 ns" { pa_in[1] Equal0~15 ctr } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.700 ns" { pa_in[1] pa_in[1]~out Equal0~15 ctr } { 0.000ns 0.000ns 1.200ns 0.000ns } { 0.000ns 0.600ns 2.100ns 0.800ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q\[0\] Uflag\[1\] clk 0.000 ns register " "Info: th for register \"q\[0\]\" (data pin = \"Uflag\[1\]\", clock pin = \"clk\") is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns clk 1 CLK PIN_37 22 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_37; Fanout = 22; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.600 ns q\[0\] 2 REG LC27 2 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC27; Fanout = 2; REG Node = 'q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { clk q[0] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { clk q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.600 ns" { clk clk~out q[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.600 ns + " "Info: + Micro hold delay of destination is 0.600 ns" {  } { { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 152 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 0.600 ns Uflag\[1\] 1 PIN PIN_44 2 " "Info: 1: + IC(0.000 ns) + CELL(0.600 ns) = 0.600 ns; Loc. = PIN_44; Fanout = 2; PIN Node = 'Uflag\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Uflag[1] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.600 ns) 2.200 ns q\[0\] 2 REG LC27 2 " "Info: 2: + IC(1.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC27; Fanout = 2; REG Node = 'q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { Uflag[1] q[0] } "NODE_NAME" } } { "ctr.vhd" "" { Text "E:/2006.3.27/ctr.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 54.55 % ) " "Info: Total cell delay = 1.200 ns ( 54.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 45.45 % ) " "Info: Total interconnect delay = 1.000 ns ( 45.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { Uflag[1] q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.200 ns" { Uflag[1] Uflag[1]~out q[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.600ns 0.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { clk q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.600 ns" { clk clk~out q[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { Uflag[1] q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.200 ns" { Uflag[1] Uflag[1]~out q[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.600ns 0.600ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 01 14:22:52 2006 " "Info: Processing ended: Fri Dec 01 14:22:52 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}