up3_clock.map.rpt

来自「在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒」· RPT 代码 · 共 245 行 · 第 1/5 页

; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM Memory Blocks                              ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                         ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                            ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------+
; UP3_CLOCK.vhd                    ; yes             ; User VHDL File  ; F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 752   ;
;     -- Combinational with no register       ; 351   ;
;     -- Register only                        ; 44    ;
;     -- Combinational with a register        ; 357   ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 405   ;
;     -- 3 input functions                    ; 85    ;
;     -- 2 input functions                    ; 206   ;
;     -- 1 input functions                    ; 11    ;
;     -- 0 input functions                    ; 1     ;