up3_clock.tan.qmsg

在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒

{ "Info" "ITDB_TSU_RESULT" "TEMP_BCD_MIND1\[2\] DipSwitch2 CLK_48MHZ 9.771 ns register " "Info: tsu for register \"TEMP_BCD_MIND1\[2\]\" (data pin = \"DipSwitch2\", clock pin = \"CLK_48MHZ\") is 9.771 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.643 ns + Longest pin register " "Info: + Longest pin to register delay is 12.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DipSwitch2 1 PIN PIN_59 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_59; Fanout = 10; PIN Node = 'DipSwitch2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DipSwitch2 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.449 ns) + CELL(0.590 ns) 10.508 ns TEMP_BCD_MIND1\[3\]~428 2 COMB LC_X25_Y6_N6 3 " "Info: 2: + IC(8.449 ns) + CELL(0.590 ns) = 10.508 ns; Loc. = LC_X25_Y6_N6; Fanout = 3; COMB Node = 'TEMP_BCD_MIND1\[3\]~428'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.039 ns" { DipSwitch2 TEMP_BCD_MIND1[3]~428 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 1262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.268 ns) + CELL(0.867 ns) 12.643 ns TEMP_BCD_MIND1\[2\] 3 REG LC_X24_Y8_N7 5 " "Info: 3: + IC(1.268 ns) + CELL(0.867 ns) = 12.643 ns; Loc. = LC_X24_Y8_N7; Fanout = 5; REG Node = 'TEMP_BCD_MIND1\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.135 ns" { TEMP_BCD_MIND1[3]~428 TEMP_BCD_MIND1[2] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 1262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.926 ns ( 23.14 % ) " "Info: Total cell delay = 2.926 ns ( 23.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.717 ns ( 76.86 % ) " "Info: Total interconnect delay = 9.717 ns ( 76.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.643 ns" { DipSwitch2 TEMP_BCD_MIND1[3]~428 TEMP_BCD_MIND1[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.643 ns" { DipSwitch2 DipSwitch2~out0 TEMP_BCD_MIND1[3]~428 TEMP_BCD_MIND1[2] } { 0.000ns 0.000ns 8.449ns 1.268ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 1262 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ destination 2.909 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_48MHZ\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 189 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 189; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns TEMP_BCD_MIND1\[2\] 2 REG LC_X24_Y8_N7 5 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X24_Y8_N7; Fanout = 5; REG Node = 'TEMP_BCD_MIND1\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.440 ns" { CLK_48MHZ TEMP_BCD_MIND1[2] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 1262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_48MHZ TEMP_BCD_MIND1[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_48MHZ CLK_48MHZ~out0 TEMP_BCD_MIND1[2] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.643 ns" { DipSwitch2 TEMP_BCD_MIND1[3]~428 TEMP_BCD_MIND1[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.643 ns" { DipSwitch2 DipSwitch2~out0 TEMP_BCD_MIND1[3]~428 TEMP_BCD_MIND1[2] } { 0.000ns 0.000ns 8.449ns 1.268ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_48MHZ TEMP_BCD_MIND1[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_48MHZ CLK_48MHZ~out0 TEMP_BCD_MIND1[2] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK_48MHZ ALARM_LED ALARM_BCD_HRD0\[2\] 15.547 ns register " "Info: tco from clock \"CLK_48MHZ\" to destination pin \"ALARM_LED\" through register \"ALARM_BCD_HRD0\[2\]\" is 15.547 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ source 2.909 ns + Longest register " "Info: + Longest clock path from clock \"CLK_48MHZ\" to source register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 189 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 189; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns ALARM_BCD_HRD0\[2\] 2 REG LC_X24_Y7_N9 6 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X24_Y7_N9; Fanout = 6; REG Node = 'ALARM_BCD_HRD0\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.440 ns" { CLK_48MHZ ALARM_BCD_HRD0[2] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 1262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_48MHZ ALARM_BCD_HRD0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_48MHZ CLK_48MHZ~out0 ALARM_BCD_HRD0[2] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 1262 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.414 ns + Longest register pin " "Info: + Longest register to pin delay is 12.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ALARM_BCD_HRD0\[2\] 1 REG LC_X24_Y7_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y7_N9; Fanout = 6; REG Node = 'ALARM_BCD_HRD0\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ALARM_BCD_HRD0[2] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 1262 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.022 ns) + CELL(0.292 ns) 2.314 ns ALARM_LED~200 2 COMB LC_X22_Y12_N2 1 " "Info: 2: + IC(2.022 ns) + CELL(0.292 ns) = 2.314 ns; Loc. = LC_X22_Y12_N2; Fanout = 1; COMB Node = 'ALARM_LED~200'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.314 ns" { ALARM_BCD_HRD0[2] ALARM_LED~200 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.228 ns) + CELL(0.442 ns) 3.984 ns ALARM_LED~202 3 COMB LC_X22_Y9_N5 1 " "Info: 3: + IC(1.228 ns) + CELL(0.442 ns) = 3.984 ns; Loc. = LC_X22_Y9_N5; Fanout = 1; COMB Node = 'ALARM_LED~202'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.670 ns" { ALARM_LED~200 ALARM_LED~202 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.114 ns) 4.513 ns ALARM_LED~204 4 COMB LC_X22_Y9_N9 1 " "Info: 4: + IC(0.415 ns) + CELL(0.114 ns) = 4.513 ns; Loc. = LC_X22_Y9_N9; Fanout = 1; COMB Node = 'ALARM_LED~204'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.529 ns" { ALARM_LED~202 ALARM_LED~204 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.590 ns) 5.530 ns ALARM_LED~205 5 COMB LC_X22_Y9_N7 1 " "Info: 5: + IC(0.427 ns) + CELL(0.590 ns) = 5.530 ns; Loc. = LC_X22_Y9_N7; Fanout = 1; COMB Node = 'ALARM_LED~205'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.017 ns" { ALARM_LED~204 ALARM_LED~205 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.292 ns) 6.264 ns ALARM_LED~206 6 COMB LC_X22_Y9_N6 1 " "Info: 6: + IC(0.442 ns) + CELL(0.292 ns) = 6.264 ns; Loc. = LC_X22_Y9_N6; Fanout = 1; COMB Node = 'ALARM_LED~206'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.734 ns" { ALARM_LED~205 ALARM_LED~206 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.026 ns) + CELL(2.124 ns) 12.414 ns ALARM_LED 7 PIN PIN_55 0 " "Info: 7: + IC(4.026 ns) + CELL(2.124 ns) = 12.414 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'ALARM_LED'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.150 ns" { ALARM_LED~206 ALARM_LED } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.854 ns ( 31.05 % ) " "Info: Total cell delay = 3.854 ns ( 31.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.560 ns ( 68.95 % ) " "Info: Total interconnect delay = 8.560 ns ( 68.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.414 ns" { ALARM_BCD_HRD0[2] ALARM_LED~200 ALARM_LED~202 ALARM_LED~204 ALARM_LED~205 ALARM_LED~206 ALARM_LED } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.414 ns" { ALARM_BCD_HRD0[2] ALARM_LED~200 ALARM_LED~202 ALARM_LED~204 ALARM_LED~205 ALARM_LED~206 ALARM_LED } { 0.000ns 2.022ns 1.228ns 0.415ns 0.427ns 0.442ns 4.026ns } { 0.000ns 0.292ns 0.442ns 0.114ns 0.590ns 0.292ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_48MHZ ALARM_BCD_HRD0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_48MHZ CLK_48MHZ~out0 ALARM_BCD_HRD0[2] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.414 ns" { ALARM_BCD_HRD0[2] ALARM_LED~200 ALARM_LED~202 ALARM_LED~204 ALARM_LED~205 ALARM_LED~206 ALARM_LED } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.414 ns" { ALARM_BCD_HRD0[2] ALARM_LED~200 ALARM_LED~202 ALARM_LED~204 ALARM_LED~205 ALARM_LED~206 ALARM_LED } { 0.000ns 2.022ns 1.228ns 0.415ns 0.427ns 0.442ns 4.026ns } { 0.000ns 0.292ns 0.442ns 0.114ns 0.590ns 0.292ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset RESET_LED 9.832 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"RESET_LED\" is 9.832 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_23 273 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 273; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.239 ns) + CELL(2.124 ns) 9.832 ns RESET_LED 2 PIN PIN_53 0 " "Info: 2: + IC(6.239 ns) + CELL(2.124 ns) = 9.832 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'RESET_LED'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.363 ns" { reset RESET_LED } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.593 ns ( 36.54 % ) " "Info: Total cell delay = 3.593 ns ( 36.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.239 ns ( 63.46 % ) " "Info: Total interconnect delay = 6.239 ns ( 63.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.832 ns" { reset RESET_LED } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.832 ns" { reset reset~out0 RESET_LED } { 0.000ns 0.000ns 6.239ns } { 0.000ns 1.469ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "R_current_state.r_check_ack8 DipSwitch1 CLK_48MHZ -2.263 ns register " "Info: th for register \"R_current_state.r_check_ack8\" (data pin = \"DipSwitch1\", clock pin = \"CLK_48MHZ\") is -2.263 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ destination 7.348 ns + Longest register " "Info: + Longest clock path from clock \"CLK_48MHZ\" to destination register is 7.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 189 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 189; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_4000HZ 2 REG LC_X8_Y10_N9 114 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 114; REG Node = 'CLK_4000HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK_48MHZ CLK_4000HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.488 ns) + CELL(0.711 ns) 7.348 ns R_current_state.r_check_ack8 3 REG LC_X15_Y9_N4 3 " "Info: 3: + IC(3.488 ns) + CELL(0.711 ns) = 7.348 ns; Loc. = LC_X15_Y9_N4; Fanout = 3; REG Node = 'R_current_state.r_check_ack8'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.199 ns" { CLK_4000HZ R_current_state.r_check_ack8 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 519 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.39 % ) " "Info: Total cell delay = 3.115 ns ( 42.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.233 ns ( 57.61 % ) " "Info: Total interconnect delay = 4.233 ns ( 57.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.348 ns" { CLK_48MHZ CLK_4000HZ R_current_state.r_check_ack8 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.348 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_4000HZ R_current_state.r_check_ack8 } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 519 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.626 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.626 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DipSwitch1 1 PIN PIN_58 80 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_58; Fanout = 80; PIN Node = 'DipSwitch1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DipSwitch1 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.290 ns) + CELL(0.867 ns) 9.626 ns R_current_state.r_check_ack8 2 REG LC_X15_Y9_N4 3 " "Info: 2: + IC(7.290 ns) + CELL(0.867 ns) = 9.626 ns; Loc. = LC_X15_Y9_N4; Fanout = 3; REG Node = 'R_current_state.r_check_ack8'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.157 ns" { DipSwitch1 R_current_state.r_check_ack8 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 519 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 24.27 % ) " "Info: Total cell delay = 2.336 ns ( 24.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.290 ns ( 75.73 % ) " "Info: Total interconnect delay = 7.290 ns ( 75.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.626 ns" { DipSwitch1 R_current_state.r_check_ack8 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.626 ns" { DipSwitch1 DipSwitch1~out0 R_current_state.r_check_ack8 } { 0.000ns 0.000ns 7.290ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.348 ns" { CLK_48MHZ CLK_4000HZ R_current_state.r_check_ack8 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.348 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_4000HZ R_current_state.r_check_ack8 } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.626 ns" { DipSwitch1 R_current_state.r_check_ack8 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.626 ns" { DipSwitch1 DipSwitch1~out0 R_current_state.r_check_ack8 } { 0.000ns 0.000ns 7.290ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}