up3_clock.tan.qmsg

在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_4000HZ " "Info: Detected ripple clock \"CLK_4000HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_4000HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_400HZ " "Info: Detected ripple clock \"CLK_400HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_400HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_48MHZ register \\READ_I2C:count1\[3\] register sda~reg0 124.12 MHz 8.057 ns Internal " "Info: Clock \"CLK_48MHZ\" has Internal fmax of 124.12 MHz between source register \"\\READ_I2C:count1\[3\]\" and destination register \"sda~reg0\" (period= 8.057 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.796 ns + Longest register register " "Info: + Longest register to register delay is 7.796 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\READ_I2C:count1\[3\] 1 REG LC_X20_Y8_N3 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y8_N3; Fanout = 11; REG Node = '\\READ_I2C:count1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { \READ_I2C:count1[3] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.953 ns) + CELL(0.590 ns) 1.543 ns Mux226~16 2 COMB LC_X19_Y8_N3 5 " "Info: 2: + IC(0.953 ns) + CELL(0.590 ns) = 1.543 ns; Loc. = LC_X19_Y8_N3; Fanout = 5; COMB Node = 'Mux226~16'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.543 ns" { \READ_I2C:count1[3] Mux226~16 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 880 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.256 ns) + CELL(0.590 ns) 3.389 ns comb~587 3 COMB LC_X16_Y8_N7 2 " "Info: 3: + IC(1.256 ns) + CELL(0.590 ns) = 3.389 ns; Loc. = LC_X16_Y8_N7; Fanout = 2; COMB Node = 'comb~587'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.846 ns" { Mux226~16 comb~587 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.752 ns) + CELL(0.590 ns) 5.731 ns Selector121~308 4 COMB LC_X21_Y9_N8 1 " "Info: 4: + IC(1.752 ns) + CELL(0.590 ns) = 5.731 ns; Loc. = LC_X21_Y9_N8; Fanout = 1; COMB Node = 'Selector121~308'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.342 ns" { comb~587 Selector121~308 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 530 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.292 ns) 6.472 ns comb~591 5 COMB LC_X21_Y9_N6 2 " "Info: 5: + IC(0.449 ns) + CELL(0.292 ns) = 6.472 ns; Loc. = LC_X21_Y9_N6; Fanout = 2; COMB Node = 'comb~591'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.741 ns" { Selector121~308 comb~591 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.457 ns) + CELL(0.867 ns) 7.796 ns sda~reg0 6 REG LC_X21_Y9_N1 1 " "Info: 6: + IC(0.457 ns) + CELL(0.867 ns) = 7.796 ns; Loc. = LC_X21_Y9_N1; Fanout = 1; REG Node = 'sda~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.324 ns" { comb~591 sda~reg0 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 519 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.929 ns ( 37.57 % ) " "Info: Total cell delay = 2.929 ns ( 37.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.867 ns ( 62.43 % ) " "Info: Total interconnect delay = 4.867 ns ( 62.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.796 ns" { \READ_I2C:count1[3] Mux226~16 comb~587 Selector121~308 comb~591 sda~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.796 ns" { \READ_I2C:count1[3] Mux226~16 comb~587 Selector121~308 comb~591 sda~reg0 } { 0.000ns 0.953ns 1.256ns 1.752ns 0.449ns 0.457ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.292ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ destination 7.359 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_48MHZ\" to destination register is 7.359 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 189 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 189; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_4000HZ 2 REG LC_X8_Y10_N9 114 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 114; REG Node = 'CLK_4000HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK_48MHZ CLK_4000HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 7.359 ns sda~reg0 3 REG LC_X21_Y9_N1 1 " "Info: 3: + IC(3.499 ns) + CELL(0.711 ns) = 7.359 ns; Loc. = LC_X21_Y9_N1; Fanout = 1; REG Node = 'sda~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.210 ns" { CLK_4000HZ sda~reg0 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 519 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.33 % ) " "Info: Total cell delay = 3.115 ns ( 42.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.244 ns ( 57.67 % ) " "Info: Total interconnect delay = 4.244 ns ( 57.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.359 ns" { CLK_48MHZ CLK_4000HZ sda~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.359 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_4000HZ sda~reg0 } { 0.000ns 0.000ns 0.745ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ source 7.359 ns - Longest register " "Info: - Longest clock path from clock \"CLK_48MHZ\" to source register is 7.359 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 189 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 189; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_4000HZ 2 REG LC_X8_Y10_N9 114 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 114; REG Node = 'CLK_4000HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK_48MHZ CLK_4000HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 7.359 ns \\READ_I2C:count1\[3\] 3 REG LC_X20_Y8_N3 11 " "Info: 3: + IC(3.499 ns) + CELL(0.711 ns) = 7.359 ns; Loc. = LC_X20_Y8_N3; Fanout = 11; REG Node = '\\READ_I2C:count1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.210 ns" { CLK_4000HZ \READ_I2C:count1[3] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.33 % ) " "Info: Total cell delay = 3.115 ns ( 42.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.244 ns ( 57.67 % ) " "Info: Total interconnect delay = 4.244 ns ( 57.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.359 ns" { CLK_48MHZ CLK_4000HZ \READ_I2C:count1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.359 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_4000HZ \READ_I2C:count1[3] } { 0.000ns 0.000ns 0.745ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.359 ns" { CLK_48MHZ CLK_4000HZ sda~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.359 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_4000HZ sda~reg0 } { 0.000ns 0.000ns 0.745ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.359 ns" { CLK_48MHZ CLK_4000HZ \READ_I2C:count1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.359 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_4000HZ \READ_I2C:count1[3] } { 0.000ns 0.000ns 0.745ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 519 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.796 ns" { \READ_I2C:count1[3] Mux226~16 comb~587 Selector121~308 comb~591 sda~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.796 ns" { \READ_I2C:count1[3] Mux226~16 comb~587 Selector121~308 comb~591 sda~reg0 } { 0.000ns 0.953ns 1.256ns 1.752ns 0.449ns 0.457ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.292ns 0.867ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.359 ns" { CLK_48MHZ CLK_4000HZ sda~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.359 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_4000HZ sda~reg0 } { 0.000ns 0.000ns 0.745ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.359 ns" { CLK_48MHZ CLK_4000HZ \READ_I2C:count1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.359 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_4000HZ \READ_I2C:count1[3] } { 0.000ns 0.000ns 0.745ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK_48MHZ 39 " "Warning: Circuit may not operate. Detected 39 non-operational path(s) clocked by clock \"CLK_48MHZ\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "BCD_SECD0\[0\] next_command.write_star1 CLK_48MHZ 2.657 ns " "Info: Found hold time violation between source  pin or register \"BCD_SECD0\[0\]\" and destination pin or register \"next_command.write_star1\" for clock \"CLK_48MHZ\" (Hold time is 2.657 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.794 ns + Largest " "Info: + Largest clock skew is 4.794 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ destination 7.736 ns + Longest register " "Info: + Longest clock path from clock \"CLK_48MHZ\" to destination register is 7.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 189 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 189; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_400HZ 2 REG LC_X9_Y10_N2 100 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X9_Y10_N2; Fanout = 100; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK_48MHZ CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.876 ns) + CELL(0.711 ns) 7.736 ns next_command.write_star1 3 REG LC_X21_Y11_N4 2 " "Info: 3: + IC(3.876 ns) + CELL(0.711 ns) = 7.736 ns; Loc. = LC_X21_Y11_N4; Fanout = 2; REG Node = 'next_command.write_star1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.587 ns" { CLK_400HZ next_command.write_star1 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 127 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.27 % ) " "Info: Total cell delay = 3.115 ns ( 40.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.621 ns ( 59.73 % ) " "Info: Total interconnect delay = 4.621 ns ( 59.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.736 ns" { CLK_48MHZ CLK_400HZ next_command.write_star1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.736 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ next_command.write_star1 } { 0.000ns 0.000ns 0.745ns 3.876ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ source 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_48MHZ\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 189 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 189; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns BCD_SECD0\[0\] 2 REG LC_X24_Y11_N9 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X24_Y11_N9; Fanout = 4; REG Node = 'BCD_SECD0\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { CLK_48MHZ BCD_SECD0[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 1184 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { CLK_48MHZ BCD_SECD0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { CLK_48MHZ CLK_48MHZ~out0 BCD_SECD0[0] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.736 ns" { CLK_48MHZ CLK_400HZ next_command.write_star1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.736 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ next_command.write_star1 } { 0.000ns 0.000ns 0.745ns 3.876ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { CLK_48MHZ BCD_SECD0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { CLK_48MHZ CLK_48MHZ~out0 BCD_SECD0[0] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 1184 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.928 ns - Shortest register register " "Info: - Shortest register to register delay is 1.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BCD_SECD0\[0\] 1 REG LC_X24_Y11_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y11_N9; Fanout = 4; REG Node = 'BCD_SECD0\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BCD_SECD0[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 1184 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.190 ns) + CELL(0.738 ns) 1.928 ns next_command.write_star1 2 REG LC_X21_Y11_N4 2 " "Info: 2: + IC(1.190 ns) + CELL(0.738 ns) = 1.928 ns; Loc. = LC_X21_Y11_N4; Fanout = 2; REG Node = 'next_command.write_star1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.928 ns" { BCD_SECD0[0] next_command.write_star1 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 127 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 38.28 % ) " "Info: Total cell delay = 0.738 ns ( 38.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.190 ns ( 61.72 % ) " "Info: Total interconnect delay = 1.190 ns ( 61.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.928 ns" { BCD_SECD0[0] next_command.write_star1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.928 ns" { BCD_SECD0[0] next_command.write_star1 } { 0.000ns 1.190ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 127 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.736 ns" { CLK_48MHZ CLK_400HZ next_command.write_star1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.736 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ next_command.write_star1 } { 0.000ns 0.000ns 0.745ns 3.876ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { CLK_48MHZ BCD_SECD0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { CLK_48MHZ CLK_48MHZ~out0 BCD_SECD0[0] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.928 ns" { BCD_SECD0[0] next_command.write_star1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.928 ns" { BCD_SECD0[0] next_command.write_star1 } { 0.000ns 1.190ns } { 0.000ns 0.738ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}