up3_clock.hier_info

在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒

CLK_48MHZ => write_day[2].CLK
CLK_48MHZ => write_day[3].CLK
CLK_48MHZ => write_day[4].CLK
CLK_48MHZ => write_day[5].CLK
CLK_48MHZ => write_day[6].CLK
CLK_48MHZ => write_day[7].CLK
CLK_48MHZ => write_day[8].CLK
CLK_48MHZ => write_hor[1].CLK
CLK_48MHZ => write_hor[2].CLK
CLK_48MHZ => write_hor[3].CLK
CLK_48MHZ => write_hor[4].CLK
CLK_48MHZ => write_hor[5].CLK
CLK_48MHZ => write_hor[6].CLK
CLK_48MHZ => write_hor[7].CLK
CLK_48MHZ => write_hor[8].CLK
CLK_48MHZ => write_min[1].CLK
CLK_48MHZ => write_min[2].CLK
CLK_48MHZ => write_min[3].CLK
CLK_48MHZ => write_min[4].CLK
CLK_48MHZ => write_min[5].CLK
CLK_48MHZ => write_min[6].CLK
CLK_48MHZ => write_min[7].CLK
CLK_48MHZ => write_min[8].CLK
CLK_48MHZ => write_sec[1].CLK
CLK_48MHZ => write_sec[2].CLK
CLK_48MHZ => write_sec[3].CLK
CLK_48MHZ => write_sec[4].CLK
CLK_48MHZ => write_sec[5].CLK
CLK_48MHZ => write_sec[6].CLK
CLK_48MHZ => write_sec[7].CLK
CLK_48MHZ => write_sec[8].CLK
CLK_48MHZ => BCD_YEAR1[0].CLK
CLK_48MHZ => BCD_YEAR1[1].CLK
CLK_48MHZ => BCD_YEAR1[2].CLK
CLK_48MHZ => BCD_YEAR1[3].CLK
CLK_48MHZ => BCD_MONTH0[0].CLK
CLK_48MHZ => BCD_MONTH0[1].CLK
CLK_48MHZ => BCD_MONTH0[2].CLK
CLK_48MHZ => BCD_MONTH0[3].CLK
CLK_48MHZ => BCD_MONTH1[0].CLK
CLK_48MHZ => BCD_MONTH1[1].CLK
CLK_48MHZ => BCD_MONTH1[2].CLK
CLK_48MHZ => BCD_MONTH1[3].CLK
CLK_48MHZ => BCD_DATE0[0].CLK
CLK_48MHZ => BCD_DATE0[1].CLK
CLK_48MHZ => BCD_DATE0[2].CLK
CLK_48MHZ => BCD_DATE0[3].CLK
CLK_48MHZ => BCD_DATE1[0].CLK
CLK_48MHZ => BCD_DATE1[1].CLK
CLK_48MHZ => BCD_DATE1[2].CLK
CLK_48MHZ => BCD_DATE1[3].CLK
CLK_48MHZ => BCD_DAY[0].CLK
CLK_48MHZ => BCD_DAY[1].CLK
CLK_48MHZ => BCD_DAY[2].CLK
CLK_48MHZ => BCD_DAY[3].CLK
CLK_48MHZ => BCD_SECD0[0].CLK
CLK_48MHZ => BCD_SECD0[1].CLK
CLK_48MHZ => BCD_SECD0[2].CLK
CLK_48MHZ => BCD_SECD0[3].CLK
CLK_48MHZ => BCD_SECD1[0].CLK
CLK_48MHZ => BCD_SECD1[1].CLK
CLK_48MHZ => BCD_SECD1[2].CLK
CLK_48MHZ => BCD_SECD1[3].CLK
CLK_48MHZ => BCD_MIND0[0].CLK
CLK_48MHZ => BCD_MIND0[1].CLK
CLK_48MHZ => BCD_MIND0[2].CLK
CLK_48MHZ => BCD_MIND0[3].CLK
CLK_48MHZ => BCD_MIND1[0].CLK
CLK_48MHZ => BCD_MIND1[1].CLK
CLK_48MHZ => BCD_MIND1[2].CLK
CLK_48MHZ => BCD_MIND1[3].CLK
CLK_48MHZ => BCD_HRD0[0].CLK
CLK_48MHZ => BCD_HRD0[1].CLK
CLK_48MHZ => BCD_HRD0[2].CLK
CLK_48MHZ => BCD_HRD0[3].CLK
CLK_48MHZ => BCD_HRD1[0].CLK
CLK_48MHZ => BCD_HRD1[1].CLK
CLK_48MHZ => BCD_HRD1[2].CLK
CLK_48MHZ => BCD_HRD1[3].CLK
CLK_48MHZ => CLK_4000HZ.CLK
CLK_48MHZ => CLK_COUNT_4000HZ[0].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[1].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[2].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[3].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[4].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[5].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[6].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[7].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[8].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[9].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[10].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[11].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[12].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[13].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[14].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[15].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[16].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[17].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[18].CLK
CLK_48MHZ => CLK_COUNT_4000HZ[19].CLK
CLK_48MHZ => CLK_400HZ.CLK
CLK_48MHZ => CLK_COUNT_400HZ[0].CLK
CLK_48MHZ => CLK_COUNT_400HZ[1].CLK
CLK_48MHZ => CLK_COUNT_400HZ[2].CLK
CLK_48MHZ => CLK_COUNT_400HZ[3].CLK
CLK_48MHZ => CLK_COUNT_400HZ[4].CLK
CLK_48MHZ => CLK_COUNT_400HZ[5].CLK
CLK_48MHZ => CLK_COUNT_400HZ[6].CLK
CLK_48MHZ => CLK_COUNT_400HZ[7].CLK
CLK_48MHZ => CLK_COUNT_400HZ[8].CLK
CLK_48MHZ => CLK_COUNT_400HZ[9].CLK
CLK_48MHZ => CLK_COUNT_400HZ[10].CLK
CLK_48MHZ => CLK_COUNT_400HZ[11].CLK
CLK_48MHZ => CLK_COUNT_400HZ[12].CLK
CLK_48MHZ => CLK_COUNT_400HZ[13].CLK
CLK_48MHZ => CLK_COUNT_400HZ[14].CLK
CLK_48MHZ => CLK_COUNT_400HZ[15].CLK
CLK_48MHZ => CLK_COUNT_400HZ[16].CLK
CLK_48MHZ => CLK_COUNT_400HZ[17].CLK
CLK_48MHZ => CLK_COUNT_400HZ[18].CLK
CLK_48MHZ => CLK_COUNT_400HZ[19].CLK
DipSwitch1 => pre_cnt~32.OUTPUTSELECT
DipSwitch1 => pre_cnt~33.OUTPUTSELECT
DipSwitch1 => pre_cnt~34.OUTPUTSELECT
DipSwitch1 => pre_cnt~35.OUTPUTSELECT
DipSwitch1 => pre_cnt~36.OUTPUTSELECT
DipSwitch1 => pre_cnt~37.OUTPUTSELECT
DipSwitch1 => pre_cnt~38.OUTPUTSELECT
DipSwitch1 => pre_cnt~39.OUTPUTSELECT
DipSwitch1 => R_current_state~0.OUTPUTSELECT
DipSwitch1 => R_current_state~1.OUTPUTSELECT
DipSwitch1 => R_current_state~2.OUTPUTSELECT
DipSwitch1 => R_current_state~3.OUTPUTSELECT
DipSwitch1 => R_current_state~4.OUTPUTSELECT
DipSwitch1 => R_current_state~5.OUTPUTSELECT
DipSwitch1 => R_current_state~6.OUTPUTSELECT
DipSwitch1 => R_current_state~7.OUTPUTSELECT
DipSwitch1 => R_current_state~8.OUTPUTSELECT
DipSwitch1 => R_current_state~9.OUTPUTSELECT
DipSwitch1 => R_current_state~10.OUTPUTSELECT
DipSwitch1 => R_current_state~11.OUTPUTSELECT
DipSwitch1 => R_current_state~12.OUTPUTSELECT
DipSwitch1 => R_current_state~13.OUTPUTSELECT
DipSwitch1 => R_current_state~14.OUTPUTSELECT
DipSwitch1 => R_current_state~15.OUTPUTSELECT
DipSwitch1 => R_current_state~16.OUTPUTSELECT
DipSwitch1 => R_current_state~17.OUTPUTSELECT
DipSwitch1 => R_current_state~18.OUTPUTSELECT
DipSwitch1 => R_current_state~19.OUTPUTSELECT
DipSwitch1 => R_current_state~20.OUTPUTSELECT
DipSwitch1 => R_current_state~21.OUTPUTSELECT
DipSwitch1 => R_current_state~22.OUTPUTSELECT
DipSwitch1 => sub_address~32.OUTPUTSELECT
DipSwitch1 => sub_address~33.OUTPUTSELECT
DipSwitch1 => sub_address~34.OUTPUTSELECT
DipSwitch1 => sub_address~35.OUTPUTSELECT
DipSwitch1 => sub_address~36.OUTPUTSELECT
DipSwitch1 => sub_address~37.OUTPUTSELECT
DipSwitch1 => sub_address~38.OUTPUTSELECT
DipSwitch1 => sub_address~39.OUTPUTSELECT
DipSwitch1 => write_slave_address~32.OUTPUTSELECT
DipSwitch1 => write_slave_address~33.OUTPUTSELECT
DipSwitch1 => write_slave_address~34.OUTPUTSELECT
DipSwitch1 => write_slave_address~35.OUTPUTSELECT
DipSwitch1 => write_slave_address~36.OUTPUTSELECT
DipSwitch1 => write_slave_address~37.OUTPUTSELECT
DipSwitch1 => write_slave_address~38.OUTPUTSELECT
DipSwitch1 => write_slave_address~39.OUTPUTSELECT
DipSwitch1 => count1~8.OUTPUTSELECT
DipSwitch1 => count1~9.OUTPUTSELECT
DipSwitch1 => count1~10.OUTPUTSELECT
DipSwitch1 => count1~11.OUTPUTSELECT
DipSwitch1 => cnt1~12.OUTPUTSELECT
DipSwitch1 => cnt1~13.OUTPUTSELECT
DipSwitch1 => cnt1~14.OUTPUTSELECT
DipSwitch1 => cnt1~15.OUTPUTSELECT
DipSwitch1 => scl~3.OUTPUTSELECT
DipSwitch1 => W_current_state~44.OUTPUTSELECT
DipSwitch1 => W_current_state~45.OUTPUTSELECT
DipSwitch1 => W_current_state~46.OUTPUTSELECT
DipSwitch1 => W_current_state~47.OUTPUTSELECT
DipSwitch1 => W_current_state~48.OUTPUTSELECT
DipSwitch1 => W_current_state~49.OUTPUTSELECT
DipSwitch1 => W_current_state~50.OUTPUTSELECT
DipSwitch1 => W_current_state~51.OUTPUTSELECT
DipSwitch1 => W_current_state~52.OUTPUTSELECT
DipSwitch1 => W_current_state~53.OUTPUTSELECT
DipSwitch1 => W_current_state~54.OUTPUTSELECT
DipSwitch1 => W_current_state~55.OUTPUTSELECT
DipSwitch1 => W_current_state~56.OUTPUTSELECT
DipSwitch1 => W_current_state~57.OUTPUTSELECT
DipSwitch1 => W_current_state~58.OUTPUTSELECT
DipSwitch1 => W_current_state~59.OUTPUTSELECT
DipSwitch1 => W_current_state~60.OUTPUTSELECT
DipSwitch1 => W_current_state~61.OUTPUTSELECT
DipSwitch1 => W_current_state~62.OUTPUTSELECT
DipSwitch1 => W_current_state~63.OUTPUTSELECT
DipSwitch1 => W_current_state~64.OUTPUTSELECT
DipSwitch1 => W_current_state~65.OUTPUTSELECT
DipSwitch1 => BCD_HRD1~2.OUTPUTSELECT
DipSwitch1 => BCD_HRD1~3.OUTPUTSELECT
DipSwitch1 => BCD_HRD0~4.OUTPUTSELECT
DipSwitch1 => BCD_HRD0~5.OUTPUTSELECT
DipSwitch1 => BCD_HRD0~6.OUTPUTSELECT
DipSwitch1 => BCD_HRD0~7.OUTPUTSELECT
DipSwitch1 => BCD_MIND1~3.OUTPUTSELECT
DipSwitch1 => BCD_MIND1~4.OUTPUTSELECT
DipSwitch1 => BCD_MIND1~5.OUTPUTSELECT
DipSwitch1 => BCD_MIND0~4.OUTPUTSELECT
DipSwitch1 => BCD_MIND0~5.OUTPUTSELECT
DipSwitch1 => BCD_MIND0~6.OUTPUTSELECT
DipSwitch1 => BCD_MIND0~7.OUTPUTSELECT
DipSwitch1 => BCD_SECD1~3.OUTPUTSELECT
DipSwitch1 => BCD_SECD1~4.OUTPUTSELECT
DipSwitch1 => BCD_SECD1~5.OUTPUTSELECT
DipSwitch1 => BCD_SECD0~4.OUTPUTSELECT
DipSwitch1 => BCD_SECD0~5.OUTPUTSELECT
DipSwitch1 => BCD_SECD0~6.OUTPUTSELECT
DipSwitch1 => BCD_SECD0~7.OUTPUTSELECT
DipSwitch1 => BCD_DAY~3.OUTPUTSELECT
DipSwitch1 => BCD_DAY~4.OUTPUTSELECT
DipSwitch1 => BCD_DAY~5.OUTPUTSELECT
DipSwitch1 => BCD_DATE1~2.OUTPUTSELECT
DipSwitch1 => BCD_DATE1~3.OUTPUTSELECT
DipSwitch1 => BCD_DATE0~4.OUTPUTSELECT
DipSwitch1 => BCD_DATE0~5.OUTPUTSELECT
DipSwitch1 => BCD_DATE0~6.OUTPUTSELECT
DipSwitch1 => BCD_DATE0~7.OUTPUTSELECT
DipSwitch1 => BCD_MONTH1~1.OUTPUTSELECT
DipSwitch1 => BCD_MONTH0~4.OUTPUTSELECT
DipSwitch1 => BCD_MONTH0~5.OUTPUTSELECT
DipSwitch1 => BCD_MONTH0~6.OUTPUTSELECT
DipSwitch1 => BCD_MONTH0~7.OUTPUTSELECT
DipSwitch1 => BCD_YEAR1~4.OUTPUTSELECT
DipSwitch1 => BCD_YEAR1~5.OUTPUTSELECT
DipSwitch1 => BCD_YEAR1~6.OUTPUTSELECT
DipSwitch1 => BCD_YEAR1~7.OUTPUTSELECT
DipSwitch1 => comb~2.OUTPUTSELECT
DipSwitch1 => comb~4.OUTPUTSELECT
DipSwitch1 => comb~5.OUTPUTSELECT
DipSwitch1 => BCD_MONTH1[1].ENA
DipSwitch1 => BCD_MONTH1[2].ENA
DipSwitch1 => BCD_MONTH1[3].ENA
DipSwitch1 => BCD_DATE1[2].ENA
DipSwitch1 => BCD_DATE1[3].ENA
DipSwitch1 => BCD_DAY[3].ENA
DipSwitch1 => BCD_SECD1[3].ENA
DipSwitch1 => BCD_MIND1[3].ENA
DipSwitch1 => BCD_HRD1[2].ENA
DipSwitch1 => BCD_HRD1[3].ENA
DipSwitch1 => FLAG.ENA
DipSwitch3 => pre_cnt~24.OUTPUTSELECT
DipSwitch3 => pre_cnt~25.OUTPUTSELECT
DipSwitch3 => pre_cnt~26.OUTPUTSELECT
DipSwitch3 => pre_cnt~27.OUTPUTSELECT
DipSwitch3 => pre_cnt~28.OUTPUTSELECT
DipSwitch3 => pre_cnt~29.OUTPUTSELECT
DipSwitch3 => pre_cnt~30.OUTPUTSELECT
DipSwitch3 => pre_cnt~31.OUTPUTSELECT
DipSwitch3 => W_current_state~22.OUTPUTSELECT
DipSwitch3 => W_current_state~23.OUTPUTSELECT
DipSwitch3 => W_current_state~24.OUTPUTSELECT
DipSwitch3 => W_current_state~25.OUTPUTSELECT
DipSwitch3 => W_current_state~26.OUTPUTSELECT
DipSwitch3 => W_current_state~27.OUTPUTSELECT
DipSwitch3 => W_current_state~28.OUTPUTSELECT
DipSwitch3 => W_current_state~29.OUTPUTSELECT
DipSwitch3 => W_current_state~30.OUTPUTSELECT
DipSwitch3 => W_current_state~31.OUTPUTSELECT
DipSwitch3 => W_current_state~32.OUTPUTSELECT
DipSwitch3 => W_current_state~33.OUTPUTSELECT
DipSwitch3 => W_current_state~34.OUTPUTSELECT
DipSwitch3 => W_current_state~35.OUTPUTSELECT
DipSwitch3 => W_current_state~36.OUTPUTSELECT
DipSwitch3 => W_current_state~37.OUTPUTSELECT
DipSwitch3 => W_current_state~38.OUTPUTSELECT
DipSwitch3 => W_current_state~39.OUTPUTSELECT
DipSwitch3 => W_current_state~40.OUTPUTSELECT
DipSwitch3 => W_current_state~41.OUTPUTSELECT
DipSwitch3 => W_current_state~42.OUTPUTSELECT
DipSwitch3 => W_current_state~43.OUTPUTSELECT
DipSwitch3 => sub_address~24.OUTPUTSELECT
DipSwitch3 => sub_address~25.OUTPUTSELECT
DipSwitch3 => sub_address~26.OUTPUTSELECT
DipSwitch3 => sub_address~27.OUTPUTSELECT
DipSwitch3 => sub_address~28.OUTPUTSELECT
DipSwitch3 => sub_address~29.OUTPUTSELECT
DipSwitch3 => sub_address~30.OUTPUTSELECT
DipSwitch3 => sub_address~31.OUTPUTSELECT
DipSwitch3 => write_slave_address~24.OUTPUTSELECT
DipSwitch3 => write_slave_address~25.OUTPUTSELECT
DipSwitch3 => write_slave_address~26.OUTPUTSELECT
DipSwitch3 => write_slave_address~27.OUTPUTSELECT
DipSwitch3 => write_slave_address~28.OUTPUTSELECT
DipSwitch3 => write_slave_address~29.OUTPUTSELECT
DipSwitch3 => write_slave_address~30.OUTPUTSELECT
DipSwitch3 => write_slave_address~31.OUTPUTSELECT
DipSwitch3 => count1~4.OUTPUTSELECT
DipSwitch3 => count1~5.OUTPUTSELECT
DipSwitch3 => count1~6.OUTPUTSELECT
DipSwitch3 => count1~7.OUTPUTSELECT
DipSwitch3 => cnt1~8.OUTPUTSELECT
DipSwitch3 => cnt1~9.OUTPUTSELECT
DipSwitch3 => cnt1~10.OUTPUTSELECT
DipSwitch3 => cnt1~11.OUTPUTSELECT
DipSwitch3 => scl~2.OUTPUTSELECT
DipSwitch3 => comb~1.IN0
PBSwitch1 => PBSwitch1_flop1.DATAIN
PBSwitch2 => PBSwitch2_flop1.DATAIN
PBSwitch3 => PBSwitch3_flop1.DATAIN
LCD_RS <= LCD_RS~reg0.DB_MAX_OUTPUT_PORT_TYPE
LCD_E <= LCD_E~reg0.DB_MAX_OUTPUT_PORT_TYPE
RESET_LED <= reset.DB_MAX_OUTPUT_PORT_TYPE
SEC_LED <= BCD_SECD0[0].DB_MAX_OUTPUT_PORT_TYPE
ALARM_LED <= ALARM_LED~1.DB_MAX_OUTPUT_PORT_TYPE
RTC_LED <= RTC_LED~reg0.DB_MAX_OUTPUT_PORT_TYPE
LCD_RW <= LCD_RW~reg0.DB_MAX_OUTPUT_PORT_TYPE
sda <= comb~6
scl <= scl~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA_BUS[0] <= comb~7
DATA_BUS[1] <= comb~8
DATA_BUS[2] <= comb~9
DATA_BUS[3] <= comb~10
DATA_BUS[4] <= comb~11
DATA_BUS[5] <= comb~12
DATA_BUS[6] <= comb~13
DATA_BUS[7] <= comb~14