up3_clock.hier_info

在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒

|UP3_CLOCK
reset => comb~3.IN0
reset => LCD_RW~reg0.ACLR
reset => LCD_RS~reg0.ACLR
reset => LCD_E~reg0.PRESET
reset => DATA_BUS_VALUE[0].ACLR
reset => DATA_BUS_VALUE[1].ACLR
reset => DATA_BUS_VALUE[2].ACLR
reset => DATA_BUS_VALUE[3].PRESET
reset => DATA_BUS_VALUE[4].PRESET
reset => DATA_BUS_VALUE[5].PRESET
reset => DATA_BUS_VALUE[6].ACLR
reset => DATA_BUS_VALUE[7].ACLR
reset => BCD_YEAR1[3].ACLR
reset => BCD_YEAR1[2].ACLR
reset => BCD_YEAR1[1].ACLR
reset => BCD_YEAR1[0].ACLR
reset => BCD_MONTH0[0].ACLR
reset => BCD_MONTH0[1].ACLR
reset => BCD_MONTH0[2].ACLR
reset => BCD_MONTH0[3].ACLR
reset => BCD_MONTH1[0].ACLR
reset => BCD_MONTH1[1].ACLR
reset => BCD_MONTH1[2].ACLR
reset => BCD_MONTH1[3].ACLR
reset => BCD_DATE0[0].ACLR
reset => BCD_DATE0[1].ACLR
reset => BCD_DATE0[2].ACLR
reset => BCD_DATE0[3].ACLR
reset => BCD_DATE1[0].ACLR
reset => BCD_DATE1[1].ACLR
reset => BCD_DATE1[2].ACLR
reset => BCD_DATE1[3].ACLR
reset => BCD_DAY[0].ACLR
reset => BCD_DAY[1].ACLR
reset => BCD_DAY[2].ACLR
reset => BCD_DAY[3].ACLR
reset => BCD_SECD0[0].ACLR
reset => BCD_SECD0[1].ACLR
reset => BCD_SECD0[2].ACLR
reset => BCD_SECD0[3].ACLR
reset => BCD_SECD1[0].ACLR
reset => BCD_SECD1[1].ACLR
reset => BCD_SECD1[2].ACLR
reset => BCD_SECD1[3].ACLR
reset => BCD_MIND0[0].ACLR
reset => BCD_MIND0[1].ACLR
reset => BCD_MIND0[2].ACLR
reset => BCD_MIND0[3].ACLR
reset => BCD_MIND1[0].ACLR
reset => BCD_MIND1[1].ACLR
reset => BCD_MIND1[2].ACLR
reset => BCD_MIND1[3].ACLR
reset => BCD_HRD0[0].ACLR
reset => BCD_HRD0[1].ACLR
reset => BCD_HRD0[2].ACLR
reset => BCD_HRD0[3].ACLR
reset => BCD_HRD1[0].ACLR
reset => BCD_HRD1[1].ACLR
reset => BCD_HRD1[2].ACLR
reset => BCD_HRD1[3].ACLR
reset => FLAG.PRESET
reset => \READ_I2C:pre_cnt[0].ACLR
reset => \READ_I2C:pre_cnt[1].ACLR
reset => \READ_I2C:pre_cnt[2].ACLR
reset => \READ_I2C:pre_cnt[3].ACLR
reset => \READ_I2C:pre_cnt[4].ACLR
reset => \READ_I2C:pre_cnt[5].ACLR
reset => \READ_I2C:pre_cnt[6].ACLR
reset => \READ_I2C:pre_cnt[7].ACLR
reset => \READ_I2C:delay_num[0].ACLR
reset => \READ_I2C:delay_num[1].ACLR
reset => \READ_I2C:delay_num[2].ACLR
reset => \READ_I2C:delay_num[3].ACLR
reset => \READ_I2C:delay_num[4].ACLR
reset => \READ_I2C:delay_num[5].ACLR
reset => \READ_I2C:delay_num[6].ACLR
reset => \READ_I2C:delay_num[7].ACLR
reset => \READ_I2C:delay_num[8].ACLR
reset => \READ_I2C:delay_num[9].ACLR
reset => \READ_I2C:delay_num[10].ACLR
reset => \READ_I2C:delay_num[11].ACLR
reset => \READ_I2C:delay_num[12].ACLR
reset => \READ_I2C:delay_num[13].ACLR
reset => \READ_I2C:delay_num[14].ACLR
reset => PBSwitch1_flop2.PRESET
reset => PBSwitch1_flop1.PRESET
reset => count1[0].ACLR
reset => count1[1].ACLR
reset => count1[2].ACLR
reset => count1[3].ACLR
reset => count1[4].ACLR
reset => count1[5].ACLR
reset => count1[6].ACLR
reset => count1[7].ACLR
reset => count1[8].ACLR
reset => count1[9].ACLR
reset => count1[10].ACLR
reset => count1[11].ACLR
reset => count1[12].ACLR
reset => count1[13].ACLR
reset => count1[14].ACLR
reset => count1[15].ACLR
reset => PBSwitch2_flop2.PRESET
reset => PBSwitch2_flop1.PRESET
reset => count2[0].ACLR
reset => count2[1].ACLR
reset => count2[2].ACLR
reset => count2[3].ACLR
reset => count2[4].ACLR
reset => count2[5].ACLR
reset => count2[6].ACLR
reset => count2[7].ACLR
reset => count2[8].ACLR
reset => count2[9].ACLR
reset => count2[10].ACLR
reset => count2[11].ACLR
reset => count2[12].ACLR
reset => count2[13].ACLR
reset => count2[14].ACLR
reset => count2[15].ACLR
reset => PBSwitch3_flop2.PRESET
reset => PBSwitch3_flop1.PRESET
reset => count3[0].ACLR
reset => count3[1].ACLR
reset => count3[2].ACLR
reset => count3[3].ACLR
reset => count3[4].ACLR
reset => count3[5].ACLR
reset => count3[6].ACLR
reset => count3[7].ACLR
reset => count3[8].ACLR
reset => count3[9].ACLR
reset => count3[10].ACLR
reset => count3[11].ACLR
reset => count3[12].ACLR
reset => count3[13].ACLR
reset => count3[14].ACLR
reset => count3[15].ACLR
reset => CLK_COUNT_4000HZ~20.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~21.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~22.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~23.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~24.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~25.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~26.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~27.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~28.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~29.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~30.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~31.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~32.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~33.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~34.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~35.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~36.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~37.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~38.OUTPUTSELECT
reset => CLK_COUNT_4000HZ~39.OUTPUTSELECT
reset => CLK_4000HZ~1.OUTPUTSELECT
reset => CLK_COUNT_400HZ~20.OUTPUTSELECT
reset => CLK_COUNT_400HZ~21.OUTPUTSELECT
reset => CLK_COUNT_400HZ~22.OUTPUTSELECT
reset => CLK_COUNT_400HZ~23.OUTPUTSELECT
reset => CLK_COUNT_400HZ~24.OUTPUTSELECT
reset => CLK_COUNT_400HZ~25.OUTPUTSELECT
reset => CLK_COUNT_400HZ~26.OUTPUTSELECT
reset => CLK_COUNT_400HZ~27.OUTPUTSELECT
reset => CLK_COUNT_400HZ~28.OUTPUTSELECT
reset => CLK_COUNT_400HZ~29.OUTPUTSELECT
reset => CLK_COUNT_400HZ~30.OUTPUTSELECT
reset => CLK_COUNT_400HZ~31.OUTPUTSELECT
reset => CLK_COUNT_400HZ~32.OUTPUTSELECT
reset => CLK_COUNT_400HZ~33.OUTPUTSELECT
reset => CLK_COUNT_400HZ~34.OUTPUTSELECT
reset => CLK_COUNT_400HZ~35.OUTPUTSELECT
reset => CLK_COUNT_400HZ~36.OUTPUTSELECT
reset => CLK_COUNT_400HZ~37.OUTPUTSELECT
reset => CLK_COUNT_400HZ~38.OUTPUTSELECT
reset => CLK_COUNT_400HZ~39.OUTPUTSELECT
reset => CLK_400HZ~1.OUTPUTSELECT
reset => RESET_LED.DATAIN
reset => scl~reg0.ENA
reset => \READ_I2C:cnt1[0].ENA
reset => \READ_I2C:cnt1[1].ENA
reset => \READ_I2C:cnt1[2].ENA
reset => \READ_I2C:cnt1[3].ENA
reset => \READ_I2C:count1[0].ENA
reset => \READ_I2C:count1[1].ENA
reset => \READ_I2C:count1[2].ENA
reset => \READ_I2C:count1[3].ENA
reset => \READ_I2C:write_slave_address[1].ENA
reset => \READ_I2C:write_slave_address[2].ENA
reset => \READ_I2C:write_slave_address[3].ENA
reset => \READ_I2C:write_slave_address[4].ENA
reset => \READ_I2C:write_slave_address[5].ENA
reset => \READ_I2C:write_slave_address[6].ENA
reset => \READ_I2C:write_slave_address[7].ENA
reset => \READ_I2C:write_slave_address[8].ENA
reset => \READ_I2C:sub_address[1].ENA
reset => \READ_I2C:sub_address[2].ENA
reset => \READ_I2C:sub_address[3].ENA
reset => \READ_I2C:sub_address[4].ENA
reset => \READ_I2C:sub_address[5].ENA
reset => \READ_I2C:sub_address[6].ENA
reset => \READ_I2C:sub_address[7].ENA
reset => \READ_I2C:sub_address[8].ENA
reset => W_current_state~67.IN1
reset => R_current_state~24.IN1
reset => next_command~6.IN1
reset => state~45.IN1
CLK_48MHZ => count3[0].CLK
CLK_48MHZ => count3[1].CLK
CLK_48MHZ => count3[2].CLK
CLK_48MHZ => count3[3].CLK
CLK_48MHZ => count3[4].CLK
CLK_48MHZ => count3[5].CLK
CLK_48MHZ => count3[6].CLK
CLK_48MHZ => count3[7].CLK
CLK_48MHZ => count3[8].CLK
CLK_48MHZ => count3[9].CLK
CLK_48MHZ => count3[10].CLK
CLK_48MHZ => count3[11].CLK
CLK_48MHZ => count3[12].CLK
CLK_48MHZ => count3[13].CLK
CLK_48MHZ => count3[14].CLK
CLK_48MHZ => count3[15].CLK
CLK_48MHZ => PBSwitch3_flop2.CLK
CLK_48MHZ => PBSwitch3_flop1.CLK
CLK_48MHZ => count2[0].CLK
CLK_48MHZ => count2[1].CLK
CLK_48MHZ => count2[2].CLK
CLK_48MHZ => count2[3].CLK
CLK_48MHZ => count2[4].CLK
CLK_48MHZ => count2[5].CLK
CLK_48MHZ => count2[6].CLK
CLK_48MHZ => count2[7].CLK
CLK_48MHZ => count2[8].CLK
CLK_48MHZ => count2[9].CLK
CLK_48MHZ => count2[10].CLK
CLK_48MHZ => count2[11].CLK
CLK_48MHZ => count2[12].CLK
CLK_48MHZ => count2[13].CLK
CLK_48MHZ => count2[14].CLK
CLK_48MHZ => count2[15].CLK
CLK_48MHZ => PBSwitch2_flop2.CLK
CLK_48MHZ => PBSwitch2_flop1.CLK
CLK_48MHZ => count1[0].CLK
CLK_48MHZ => count1[1].CLK
CLK_48MHZ => count1[2].CLK
CLK_48MHZ => count1[3].CLK
CLK_48MHZ => count1[4].CLK
CLK_48MHZ => count1[5].CLK
CLK_48MHZ => count1[6].CLK
CLK_48MHZ => count1[7].CLK
CLK_48MHZ => count1[8].CLK
CLK_48MHZ => count1[9].CLK
CLK_48MHZ => count1[10].CLK
CLK_48MHZ => count1[11].CLK
CLK_48MHZ => count1[12].CLK
CLK_48MHZ => count1[13].CLK
CLK_48MHZ => count1[14].CLK
CLK_48MHZ => count1[15].CLK
CLK_48MHZ => PBSwitch1_flop2.CLK
CLK_48MHZ => PBSwitch1_flop1.CLK
CLK_48MHZ => ALARM_BCD_HRD1[0].CLK
CLK_48MHZ => ALARM_BCD_HRD1[1].CLK
CLK_48MHZ => ALARM_BCD_HRD1[2].CLK
CLK_48MHZ => ALARM_BCD_HRD1[3].CLK
CLK_48MHZ => ALARM_BCD_HRD0[0].CLK
CLK_48MHZ => ALARM_BCD_HRD0[1].CLK
CLK_48MHZ => ALARM_BCD_HRD0[2].CLK
CLK_48MHZ => ALARM_BCD_HRD0[3].CLK
CLK_48MHZ => ALARM_BCD_MIND1[0].CLK
CLK_48MHZ => ALARM_BCD_MIND1[1].CLK
CLK_48MHZ => ALARM_BCD_MIND1[2].CLK
CLK_48MHZ => ALARM_BCD_MIND1[3].CLK
CLK_48MHZ => ALARM_BCD_MIND0[0].CLK
CLK_48MHZ => ALARM_BCD_MIND0[1].CLK
CLK_48MHZ => ALARM_BCD_MIND0[2].CLK
CLK_48MHZ => ALARM_BCD_MIND0[3].CLK
CLK_48MHZ => TEMP_BCD_HRD1[0].CLK
CLK_48MHZ => TEMP_BCD_HRD1[1].CLK
CLK_48MHZ => TEMP_BCD_HRD1[2].CLK
CLK_48MHZ => TEMP_BCD_HRD1[3].CLK
CLK_48MHZ => TEMP_BCD_HRD0[0].CLK
CLK_48MHZ => TEMP_BCD_HRD0[1].CLK
CLK_48MHZ => TEMP_BCD_HRD0[2].CLK
CLK_48MHZ => TEMP_BCD_HRD0[3].CLK
CLK_48MHZ => TEMP_BCD_MIND1[0].CLK
CLK_48MHZ => TEMP_BCD_MIND1[1].CLK
CLK_48MHZ => TEMP_BCD_MIND1[2].CLK
CLK_48MHZ => TEMP_BCD_MIND1[3].CLK
CLK_48MHZ => TEMP_BCD_MIND0[0].CLK
CLK_48MHZ => TEMP_BCD_MIND0[1].CLK
CLK_48MHZ => TEMP_BCD_MIND0[2].CLK
CLK_48MHZ => TEMP_BCD_MIND0[3].CLK
CLK_48MHZ => TEMP_BCD_SECD1[0].CLK
CLK_48MHZ => TEMP_BCD_SECD1[1].CLK
CLK_48MHZ => TEMP_BCD_SECD1[2].CLK
CLK_48MHZ => TEMP_BCD_SECD1[3].CLK
CLK_48MHZ => TEMP_BCD_SECD0[0].CLK
CLK_48MHZ => TEMP_BCD_SECD0[1].CLK
CLK_48MHZ => TEMP_BCD_SECD0[2].CLK
CLK_48MHZ => TEMP_BCD_SECD0[3].CLK
CLK_48MHZ => write_year[1].CLK
CLK_48MHZ => write_year[2].CLK
CLK_48MHZ => write_year[3].CLK
CLK_48MHZ => write_year[4].CLK
CLK_48MHZ => write_year[5].CLK
CLK_48MHZ => write_year[6].CLK
CLK_48MHZ => write_year[7].CLK
CLK_48MHZ => write_year[8].CLK
CLK_48MHZ => write_month[1].CLK
CLK_48MHZ => write_month[2].CLK
CLK_48MHZ => write_month[3].CLK
CLK_48MHZ => write_month[4].CLK
CLK_48MHZ => write_month[5].CLK
CLK_48MHZ => write_month[6].CLK
CLK_48MHZ => write_month[7].CLK
CLK_48MHZ => write_month[8].CLK
CLK_48MHZ => write_date[1].CLK
CLK_48MHZ => write_date[2].CLK
CLK_48MHZ => write_date[3].CLK
CLK_48MHZ => write_date[4].CLK
CLK_48MHZ => write_date[5].CLK
CLK_48MHZ => write_date[6].CLK
CLK_48MHZ => write_date[7].CLK
CLK_48MHZ => write_date[8].CLK
CLK_48MHZ => write_day[1].CLK