up3_clock.fit.qmsg

在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 9 " "Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 9%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x12_y0 x23_y10 " "Info: The peak interconnect region extends from location x12_y0 to location x23_y10" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Info: Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "8 " "Warning: Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[0\] a permanently enabled " "Info: Pin DATA_BUS\[0\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[1\] a permanently enabled " "Info: Pin DATA_BUS\[1\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[2\] a permanently enabled " "Info: Pin DATA_BUS\[2\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[3\] a permanently enabled " "Info: Pin DATA_BUS\[3\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[4\] a permanently enabled " "Info: Pin DATA_BUS\[4\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[5\] a permanently enabled " "Info: Pin DATA_BUS\[5\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[6\] a permanently enabled " "Info: Pin DATA_BUS\[6\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[7\] a permanently enabled " "Info: Pin DATA_BUS\[7\] has a permanently enabled output enable" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA_BUS[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_RW GND " "Info: Pin LCD_RW has GND driving its datain port" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_RW } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_RW } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "sda~en " "Info: Following pins have the same output enable: sda~en" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sda LVTTL " "Info: Type bidirectional pin sda uses the LVTTL I/O standard" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 14 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sda" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 16 23:47:05 2008 " "Info: Processing ended: Mon Jun 16 23:47:05 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Info: Elapsed time: 00:00:21" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.fit.smsg " "Info: Generated suppressed messages file F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}