up3_clock.fit.qmsg

在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒

{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "reset " "Info: Pin \"reset\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.801 ns register register " "Info: Estimated most critical path is register to register delay of 7.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\READ_I2C:pre_cnt\[2\] 1 REG LAB_X23_Y6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X23_Y6; Fanout = 3; REG Node = '\\READ_I2C:pre_cnt\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { \READ_I2C:pre_cnt[2] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.698 ns) + CELL(0.575 ns) 1.273 ns Add3~180COUT1_192 2 COMB LAB_X22_Y6 2 " "Info: 2: + IC(0.698 ns) + CELL(0.575 ns) = 1.273 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Add3~180COUT1_192'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.273 ns" { \READ_I2C:pre_cnt[2] Add3~180COUT1_192 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.353 ns Add3~182COUT1 3 COMB LAB_X22_Y6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.353 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Add3~182COUT1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { Add3~180COUT1_192 Add3~182COUT1 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.611 ns Add3~186 4 COMB LAB_X22_Y6 3 " "Info: 4: + IC(0.000 ns) + CELL(0.258 ns) = 1.611 ns; Loc. = LAB_X22_Y6; Fanout = 3; COMB Node = 'Add3~186'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { Add3~182COUT1 Add3~186 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.290 ns Add3~187 5 COMB LAB_X22_Y6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.679 ns) = 2.290 ns; Loc. = LAB_X22_Y6; Fanout = 2; COMB Node = 'Add3~187'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.679 ns" { Add3~186 Add3~187 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.442 ns) 3.182 ns Equal1~82 6 COMB LAB_X21_Y6 1 " "Info: 6: + IC(0.450 ns) + CELL(0.442 ns) = 3.182 ns; Loc. = LAB_X21_Y6; Fanout = 1; COMB Node = 'Equal1~82'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.892 ns" { Add3~187 Equal1~82 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 3.835 ns Equal1~83 7 COMB LAB_X21_Y6 11 " "Info: 7: + IC(0.539 ns) + CELL(0.114 ns) = 3.835 ns; Loc. = LAB_X21_Y6; Fanout = 11; COMB Node = 'Equal1~83'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Equal1~82 Equal1~83 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 4.488 ns Selector120~298 8 COMB LAB_X21_Y6 1 " "Info: 8: + IC(0.539 ns) + CELL(0.114 ns) = 4.488 ns; Loc. = LAB_X21_Y6; Fanout = 1; COMB Node = 'Selector120~298'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Equal1~83 Selector120~298 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 853 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.442 ns) 5.853 ns Selector120~299 9 COMB LAB_X21_Y9 1 " "Info: 9: + IC(0.923 ns) + CELL(0.442 ns) = 5.853 ns; Loc. = LAB_X21_Y9; Fanout = 1; COMB Node = 'Selector120~299'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.365 ns" { Selector120~298 Selector120~299 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 853 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 6.506 ns comb~591 10 COMB LAB_X21_Y9 2 " "Info: 10: + IC(0.539 ns) + CELL(0.114 ns) = 6.506 ns; Loc. = LAB_X21_Y9; Fanout = 2; COMB Node = 'comb~591'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Selector120~299 comb~591 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.867 ns) 7.801 ns sda~reg0 11 REG LAB_X21_Y9 1 " "Info: 11: + IC(0.428 ns) + CELL(0.867 ns) = 7.801 ns; Loc. = LAB_X21_Y9; Fanout = 1; REG Node = 'sda~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.295 ns" { comb~591 sda~reg0 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 519 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.685 ns ( 47.24 % ) " "Info: Total cell delay = 3.685 ns ( 47.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.116 ns ( 52.76 % ) " "Info: Total interconnect delay = 4.116 ns ( 52.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.801 ns" { \READ_I2C:pre_cnt[2] Add3~180COUT1_192 Add3~182COUT1 Add3~186 Add3~187 Equal1~82 Equal1~83 Selector120~298 Selector120~299 comb~591 sda~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}