up3_clock.fit.qmsg

在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 16 23:46:45 2008 " "Info: Processing started: Mon Jun 16 23:46:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off UP3_CLOCK -c UP3_CLOCK " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off UP3_CLOCK -c UP3_CLOCK" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "UP3_CLOCK EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"UP3_CLOCK\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK_48MHZ Global clock in PIN 29 " "Info: Automatically promoted signal \"CLK_48MHZ\" to use Global clock in PIN 29" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "CLK_4000HZ Global clock " "Info: Automatically promoted some destinations of signal \"CLK_4000HZ\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_4000HZ " "Info: Destination \"CLK_4000HZ\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "CLK_400HZ Global clock " "Info: Automatically promoted some destinations of signal \"CLK_400HZ\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_400HZ " "Info: Destination \"CLK_400HZ\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RESET_LED " "Info: Destination \"RESET_LED\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "scl~reg0 " "Info: Destination \"scl~reg0\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 519 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_400HZ " "Info: Destination \"CLK_400HZ\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RTC_LED~1 " "Info: Destination \"RTC_LED~1\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 12 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_4000HZ " "Info: Destination \"CLK_4000HZ\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 35 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RTC_SEC\[1\]~983 " "Info: Destination \"RTC_SEC\[1\]~983\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 519 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~580 " "Info: Destination \"comb~580\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\READ_I2C:count1\[0\]~166 " "Info: Destination \"\\READ_I2C:count1\[0\]~166\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_COUNT_400HZ\[0\]~305 " "Info: Destination \"CLK_COUNT_400HZ\[0\]~305\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 107 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\READ_I2C:cnt1\[0\]~287 " "Info: Destination \"\\READ_I2C:cnt1\[0\]~287\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "UP3_CLOCK.vhd" "" { Text "F:/课件/EDA实验代码/实验5-时钟设计-最终版/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}