📄 up3_clock.vhd
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when W_stop=>count1:=count1+1; --产生停止信号
case count1 is
when 1=>sda<='0';
when 3=>scl<='1';
when 6=>sda<='1';
when 8=>count1:=0;
W_current_state<=W_delay;
when others=>null;
end case;
when W_delay=>delay_num:=delay_num+1;
case delay_num is
when 4000 =>RTC_LED<='1';
when 20000=>RTC_LED<='0';
delay_num:=0;
W_current_state<=W_prepare;
when others=>null;
end case;
when others=>null;
end case;
end if;
end if;
end if;
end process;
PROCESS( CLK_48MHZ, reset )
BEGIN
if reset='0' then
BCD_HRD1 <= X"0";
BCD_HRD0 <= X"0";
BCD_MIND1 <= X"0";
BCD_MIND0 <= X"0";
BCD_SECD1 <= X"0";
BCD_SECD0 <= X"0";
BCD_DAY <= X"0";
BCD_DATE1 <= X"0";
BCD_DATE0 <= X"0";
BCD_MONTH1<= X"0";
BCD_MONTH0<= X"0";
BCD_YEAR1 <= X"0";
BCD_YEAR0 <= X"0";
elsif rising_edge(CLK_48MHZ) then
IF DipSwitch1 = '1' THEN
IF FLAG = '1' THEN
BCD_HRD1(1 DOWNTO 0) <= RTC_HOR(6 DOWNTO 5);
BCD_HRD0(3 DOWNTO 0) <= RTC_HOR(4 DOWNTO 1);
BCD_MIND1(2 DOWNTO 0) <= RTC_MIN(7 DOWNTO 5);
BCD_MIND0(3 DOWNTO 0) <= RTC_MIN(4 DOWNTO 1);
BCD_SECD1(2 DOWNTO 0) <= RTC_SEC(7 DOWNTO 5);
BCD_SECD0(3 DOWNTO 0) <= RTC_SEC(4 DOWNTO 1);
BCD_DAY(2 DOWNTO 0) <= RTC_DAY(3 DOWNTO 1);
BCD_DATE1(1 DOWNTO 0) <= RTC_DATE(6 DOWNTO 5);
BCD_DATE0(3 DOWNTO 0) <= RTC_DATE(4 DOWNTO 1);
BCD_MONTH1(0) <= RTC_MONTH(5);
BCD_MONTH0(3 DOWNTO 0)<= RTC_MONTH(4 DOWNTO 1);
BCD_YEAR1(3 DOWNTO 0) <= RTC_YEAR (8 DOWNTO 5);
BCD_YEAR0(3 DOWNTO 0) <= RTC_YEAR (4 DOWNTO 1);
END IF;
ELSE
BCD_SECD0 <= TEMP_BCD_SECD0;
BCD_SECD1 <= TEMP_BCD_SECD1;
BCD_MIND0 <= TEMP_BCD_MIND0;
BCD_MIND1 <= TEMP_BCD_MIND1;
BCD_HRD0 <= TEMP_BCD_HRD0;
BCD_HRD1 <= TEMP_BCD_HRD1;
BCD_DAY <= "0011";
BCD_DATE1 <= "0000";
BCD_DATE0 <= "0100";
BCD_MONTH1<= "0000";
BCD_MONTH0<= "0110";
BCD_YEAR1 <= "0000";
BCD_YEAR0 <= "1000";
END IF;
END IF;
END PROCESS;
zhuanhuan: PROCESS( CLK_48MHZ )
begin
if rising_edge(CLK_48MHZ) then
write_sec(4 DOWNTO 1) <= TEMP_BCD_SECD0(3 DOWNTO 0);
write_sec(7 DOWNTO 5) <= TEMP_BCD_SECD1(2 DOWNTO 0);
write_min(4 DOWNTO 1) <= TEMP_BCD_MIND0(3 DOWNTO 0);
write_min(7 DOWNTO 5) <= TEMP_BCD_MIND1(2 DOWNTO 0);
write_hor(4 DOWNTO 1) <= TEMP_BCD_HRD0(3 DOWNTO 0);
write_hor(6 DOWNTO 5) <= TEMP_BCD_HRD1(1 DOWNTO 0);
write_hor(8 DOWNTO 7)<="00";
write_sec(8) <='0';
write_min(8) <='0';
write_day (8 DOWNTO 1) <= "00000011";
write_date (8 DOWNTO 1) <= "00000100";
write_month(8 DOWNTO 1) <= "00000110";
write_year (8 DOWNTO 1) <= "00001000";
end if;
end process;
--////////////////////////////////////////////////////////////////////////////////////
--////////////////////////////////////////////////////////////////////////////////////
--////////////////////////////////////////////////////////////////////////////////////
--////////////////////////////////////////////////////////////////////////////////////
--////////////////////////////////////////////////////////////////////////////////////
count: PROCESS (CLK_48MHZ,PB1_valid,PB2_valid,PB3_valid)
BEGIN
IF rising_edge( CLK_48MHZ ) THEN
IF DipSwitch2 = '1' THEN
IF PB1_valid = '1' THEN
IF( TEMP_BCD_SECD0 < 9 ) THEN
TEMP_BCD_SECD0 <= TEMP_BCD_SECD0 + 1;
ELSIF( TEMP_BCD_SECD1 <5 ) THEN
TEMP_BCD_SECD0 <= "0000";
TEMP_BCD_SECD1 <= TEMP_BCD_SECD1 +1 ;
ELSE
TEMP_BCD_SECD0 <= "0000";
TEMP_BCD_SECD1 <= "0000";
END IF;
ELSIF PB2_valid = '1' THEN
IF( TEMP_BCD_MIND0 < 9 ) THEN
TEMP_BCD_MIND0 <= TEMP_BCD_MIND0 + 1;
ELSIF( TEMP_BCD_MIND1 <5 ) THEN
TEMP_BCD_MIND0 <= "0000";
TEMP_BCD_MIND1 <= TEMP_BCD_MIND1 + 1;
ELSE
TEMP_BCD_MIND0 <= "0000";
TEMP_BCD_MIND1 <= "0000";
END IF;
ELSIF PB3_valid = '1' THEN
IF( TEMP_BCD_HRD0 < 9 AND NOT((TEMP_BCD_HRD1 >= 2) AND (TEMP_BCD_HRD0 >= 3))) THEN
TEMP_BCD_HRD0 <= TEMP_BCD_HRD0 + 1;
ELSIF( NOT((TEMP_BCD_HRD1 >= 2) AND (TEMP_BCD_HRD0 >= 3))) THEN
TEMP_BCD_HRD0 <= "0000";
TEMP_BCD_HRD1 <= TEMP_BCD_HRD1 + 1;
ELSE
TEMP_BCD_HRD0 <= "0000";
TEMP_BCD_HRD1 <= "0000";
END IF;
END IF;
ELSE
IF PB2_valid = '1' THEN
IF( ALARM_BCD_MIND0 < 9 ) THEN
ALARM_BCD_MIND0 <= ALARM_BCD_MIND0 + 1;
ELSIF( ALARM_BCD_MIND1 <5 ) THEN
ALARM_BCD_MIND0 <= "0000";
ALARM_BCD_MIND1 <= ALARM_BCD_MIND1 + 1;
ELSE
ALARM_BCD_MIND0 <= "0000";
ALARM_BCD_MIND1 <= "0000";
END IF;
ELSIF PB3_valid = '1' THEN
IF( ALARM_BCD_HRD0 < 9 AND NOT((ALARM_BCD_HRD1 >= 2) AND (ALARM_BCD_HRD0 >= 3))) THEN
ALARM_BCD_HRD0 <= ALARM_BCD_HRD0 + 1;
ELSIF( NOT((ALARM_BCD_HRD1 >= 2) AND (ALARM_BCD_HRD0 >= 3))) THEN
ALARM_BCD_HRD0 <= "0000";
ALARM_BCD_HRD1 <= ALARM_BCD_HRD1 + 1;
ELSE
ALARM_BCD_HRD0 <= "0000";
ALARM_BCD_HRD1 <= "0000";
END IF;
END IF;
END IF;
END IF;
END PROCESS;
ALARM: PROCESS ( CLK_48MHZ )
BEGIN
IF ( BCD_MIND0 = 0 AND BCD_MIND1 =0) THEN
IF ( BCD_SECD0 < 4 AND BCD_SECD1 = 0 ) THEN
ALARM_LED <= '1';
ELSE ALARM_LED <= '0';
END IF;
ELSIF( ALARM_BCD_HRD1 = BCD_HRD1 AND ALARM_BCD_HRD0 = BCD_HRD0 AND ALARM_BCD_MIND1 = BCD_MIND1 AND ALARM_BCD_MIND0 = BCD_MIND0) THEN
IF ( BCD_SECD0 < 8 AND BCD_SECD1 = 0) THEN
ALARM_LED <= '1';
ELSE ALARM_LED <= '0';
END IF;
ELSE
ALARM_LED <= '0';
END IF;
END PROCESS;
---/////////////////////////////////////////////////////////////////////////////////////////////
---////////////////////////////////////////////////////////////////////////////////////////////
PB1_flop: process (CLK_48MHZ, reset)
begin
if reset = '0' then
PBSwitch1_flop1 <= '1';
PBSwitch1_flop2 <= '1';
elsif rising_edge (CLK_48MHZ) then
PBSwitch1_flop1 <= PBSwitch1;
PBSwitch1_flop2 <= PBSwitch1_flop1;
end if;
end process;
--********************************************************************************************
-- This process module generates stable pulse
--********************************************************************************************
PB1_pulse: process (PBSwitch1, PBSwitch1_flop1, PBSwitch1_flop2)
begin
PB1_PulseOut <= PBSwitch1_flop2 and (not PBSwitch1_flop1);
end process;
--********************************************************************************************
-- Debounce Logic
--********************************************************************************************
PB1_debounce: process (CLK_48MHZ, reset)
begin
if reset = '0' then
count1 <= (others => '0');
elsif rising_edge (CLK_48MHZ) then
if (PBSwitch1_flop1 = '0') then
if (PB1_PulseOut = '1') then
count1 <= debounce_count;
else
if (count1 = mincount) then
count1 <= (others => '0');
else
count1 <= count1 - 1;
end if;
end if;
else
count1 <= (others => '0');
end if;
end if;
end process;
PB1_out: process (count1)
begin
case count1 is
when "0000000000000001" => if (PB1_PulseOut = '0') then
PB1_valid <= '1';
else
PB1_valid <= '0';
end if;
when others => PB1_valid <= '0';
end case;
end process;
---/////////////////////////////////////////////////////////////////////////////////////////////
---////////////////////////////////////////////////////////////////////////////////////////////
PB2_flop: process (CLK_48MHZ, reset)
begin
if reset = '0' then
PBSwitch2_flop1 <= '1';
PBSwitch2_flop2 <= '1';
elsif rising_edge (CLK_48MHZ) then
PBSwitch2_flop1 <= PBSwitch2;
PBSwitch2_flop2 <= PBSwitch2_flop1;
end if;
end process;
--********************************************************************************************
-- This process module generates stable pulse
--********************************************************************************************
PB2_pulse: process (PBSwitch2, PBSwitch2_flop1, PBSwitch2_flop2)
begin
PB2_PulseOut <= PBSwitch2_flop2 and (not PBSwitch2_flop1);
end process;
--********************************************************************************************
-- Debounce Logic
--********************************************************************************************
PB2_debounce: process (CLK_48MHZ, reset)
begin
if reset = '0' then
count2 <= (others => '0');
elsif rising_edge (CLK_48MHZ) then
if (PBSwitch2_flop1 = '0') then
if (PB2_PulseOut = '1') then
count2 <= debounce_count;
else
if (count2 = mincount) then
count2 <= (others => '0');
else
count2 <= count2 - 1;
end if;
end if;
else
count2 <= (others => '0');
end if;
end if;
end process;
PB2_out: process (count2)
begin
case count2 is
when "0000000000000001" => if (PB2_PulseOut = '0') then
PB2_valid <= '1';
else
PB2_valid <= '0';
end if;
when others => PB2_valid <= '0';
end case;
end process;
---/////////////////////////////////////////////////////////////////////////////////////////////
---////////////////////////////////////////////////////////////////////////////////////////////
PB3_flop: process (CLK_48MHZ, reset)
begin
if reset = '0' then
PBSwitch3_flop1 <= '1';
PBSwitch3_flop2 <= '1';
elsif rising_edge (CLK_48MHZ) then
PBSwitch3_flop1 <= PBSwitch3;
PBSwitch3_flop2 <= PBSwitch3_flop1;
end if;
end process;
--********************************************************************************************
-- This process module generates stable pulse
--********************************************************************************************
PB3_pulse: process (PBSwitch3, PBSwitch3_flop1, PBSwitch3_flop2)
begin
PB3_PulseOut <= PBSwitch3_flop2 and (not PBSwitch3_flop1);
end process;
--********************************************************************************************
-- Debounce Logic
--********************************************************************************************
PB3_debounce: process (CLK_48MHZ, reset)
begin
if reset = '0' then
count3 <= (others => '0');
elsif rising_edge (CLK_48MHZ) then
if (PBSwitch3_flop1 = '0') then
if (PB3_PulseOut = '1') then
count3 <= debounce_count;
else
if (count3 = mincount) then
count3 <= (others => '0');
else
count3 <= count3 - 1;
end if;
end if;
else
count3 <= (others => '0');
end if;
end if;
end process;
PB3_out: process (count3)
begin
case count3 is
when "0000000000000001" => if (PB3_PulseOut = '0') then
PB3_valid <= '1';
else
PB3_valid <= '0';
end if;
when others => PB3_valid <= '0';
end case;
end process;
---///////////////////////////////////////////////////////////////////////////////////
END a;
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