📄 up3_clock.vhd
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LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & "1000";--BCD_YEAR0;
state <= TOGGLE_E;
next_command <= WRITE_CHAR15;
WHEN WRITE_CHAR15 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"2E";
state <= TOGGLE_E;
next_command <= WRITE_CHAR16;
WHEN WRITE_CHAR16 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_MONTH1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR17;
WHEN WRITE_CHAR17 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_MONTH0;
state <= TOGGLE_E;
next_command <= WRITE_CHAR18;
WHEN WRITE_CHAR18 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"2E";
state <= TOGGLE_E;
next_command <= WRITE_CHAR19;
WHEN WRITE_CHAR19 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_DATE1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR20;
WHEN WRITE_CHAR20 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_DATE0;
state <= TOGGLE_E;
next_command <= WRITE_BLANK3;
WHEN WRITE_BLANK3 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"2A";
state <= TOGGLE_E;
next_command <= WRITE_CHAR21;
WHEN WRITE_CHAR21 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & ALARM_BCD_HRD1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR22;
WHEN WRITE_CHAR22 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & ALARM_BCD_HRD0;
state <= TOGGLE_E;
next_command <= WRITE_CHAR23;
WHEN WRITE_CHAR23 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3A";
state <= TOGGLE_E;
next_command <= WRITE_CHAR24;
WHEN WRITE_CHAR24 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & ALARM_BCD_MIND1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR25;
WHEN WRITE_CHAR25 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & ALARM_BCD_MIND0;
state <= TOGGLE_E;
next_command <= RETURN_HOME;
-- Return write address to first character postion
WHEN RETURN_HOME =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"80";
state <= TOGGLE_E;
next_command <= WRITE_CHART;
-- The next two states occur at the end of each command to the LCD
-- Toggle E line - falling edge loads inst/data to LCD controller
WHEN TOGGLE_E =>
LCD_E <= '0';
state <= HOLD;
-- Hold LCD inst/data valid after falling edge of E line
WHEN HOLD =>state <= next_command;
WHEN OTHERS =>state<= RESET1;
END CASE;
END IF;
END PROCESS;
--////////////////////////////////////////////////////////////////////////////////////
--////////////////////////////////////////////////////////////////////////////////////
--////////////////////////////////////////////////////////////////////////////////////
--////////////////////////////////////////////////////////////////////////////////////
READ_I2C :process(CLK_4000HZ,reset) --进程2，状态机的转换
variable read_slave_address,write_slave_address,sub_address :std_logic_vector(8 downto 1);
variable pre_cnt :std_logic_vector(7 downto 0);
variable cnt1 :integer range 0 to 8;
variable count1 :integer range 0 to 8;
variable delay_num :integer range 0 to 20000;
begin
if reset='0' then
delay_num:=0;
pre_cnt:="00000000";
R_current_state<=R_prepare;
W_current_state<=W_prepare;
FLAG<='1';
elsif rising_edge(CLK_4000HZ) then
if( DipSwitch1 = '1' ) then
case R_current_state is
when R_prepare=>pre_cnt:=pre_cnt+1; --准备状态，等各个器件复位
if pre_cnt="00000010" then
pre_cnt:="00000000";
R_current_state<=R_start;
sub_address:="00000000";
read_slave_address :="11010001";
write_slave_address:="11010000";
count1:=0;
cnt1:=8;
sda<='1';
scl<='1';
else R_current_state<=R_prepare;
end if;
when R_start=>count1:=count1+1; --起始信号产生状态
case count1 is
when 1=>sda<='1';
when 3=>scl<='1';
when 5=>sda<='0';
when 7=>scl<='0';
when 8=>count1:=0;
R_current_state<=R_transmit_slave_address;
when others=>null;
end case;
when R_transmit_slave_address=>count1:=count1+1; --发送器件从地址
case count1 is
when 1=>sda<=write_slave_address(cnt1);
when 3=>scl<='1';
when 7=>scl<='0';
when 8=>cnt1:=cnt1-1;
count1:=0;
if cnt1=0 then
cnt1:=8;
R_current_state<=R_check_ack1;
else R_current_state<=R_transmit_slave_address;
end if;
when others=>null;
end case;
when R_check_ack1=>count1:=count1+1; --查询应答信号
case count1 is
when 1 =>sda<='Z';
when 3 =>scl<='1';
when 5 =>if sda = '0' then
R_current_state<=R_check_ack1;
else
R_current_state<=R_prepare;
end if;
when 7 =>scl<='0';
when 8 =>R_current_state<=R_transmit_sub_address;
count1:=0;
when others=>null;
end case;
when R_transmit_sub_address=>count1:=count1+1; --发送器件子地址
case count1 is
when 1=>sda<=sub_address(cnt1);
when 3=>scl<='1';
when 7=>scl<='0';
when 8=>cnt1:=cnt1-1;
count1:=0;
if cnt1=0 then
cnt1:=8;
R_current_state<=R_check_ack2;
else R_current_state<=R_transmit_sub_address;
end if;
when others=>null;
end case;
when R_check_ack2=>count1:=count1+1; --查询应答信号
case count1 is
when 1 =>sda<='Z';
when 3 =>scl<='1';
when 5 =>if sda = '0' then
R_current_state<=R_check_ack2;
else
R_current_state<=R_prepare;
end if;
when 7 =>scl<='0';
when 8 =>R_current_state<=R_start1;
count1:=0;
when others=>null;
end case;
when R_start1=>count1:=count1+1; --重新起始信号产生状态
case count1 is
when 1=> sda<='1';
when 3=> scl<='1';
when 5=> sda<='0';
when 7=> scl<='0';
when 8=> count1:=0;
R_current_state<=R_transmit_read;
when others=>null;
end case;
when R_transmit_read=>count1:=count1+1; --发送器件从地址
case count1 is
when 1=>sda<=read_slave_address(cnt1);
when 3=>scl<='1';
when 7=>scl<='0';
when 8=>cnt1:=cnt1-1;
count1:=0;
if cnt1=0 then
cnt1:=8;
R_current_state<=R_check_ack3;
else R_current_state<=R_transmit_read;
end if;
when others=>null;
end case;
when R_check_ack3=>count1:=count1+1; --查询应答信号
case count1 is
when 1 =>sda<='Z';
when 3 =>scl<='1';
when 5 =>if sda = '0' then
R_current_state<=R_check_ack3;
else
R_current_state<=R_prepare;
end if;
when 7 =>scl<='0';
when 8 =>R_current_state<=R_read_data1;
count1:=0;
when others=>null;
end case;
when R_read_data1=>count1:=count1+1;FLAG<='0'; --读操作
case count1 is
when 1=>sda<='Z';
when 3=>scl<='1';
when 5=>RTC_SEC(cnt1)<=sda;
when 7=>scl<='0';
when 8=>cnt1:=cnt1-1;
count1:=0;
if cnt1=0 then
cnt1:=8;
R_current_state<=R_check_ack4;
FLAG<='1';
else R_current_state<=R_read_data1;
end if;
when others=>null;
end case;
when R_check_ack4=>count1:=count1+1; --查询应答信号
case count1 is
when 1 =>sda<='0';
when 3 =>scl<='1';
when 7 =>scl<='0';
when 8 =>R_current_state<=R_read_data2;
count1:=0;
when others=>null;
end case;
when R_read_data2=>count1:=count1+1;FLAG<='0'; --读操作
case count1 is
when 1=>sda<='Z';
when 3=>scl<='1';
when 5=>RTC_MIN(cnt1)<=sda;
when 7=>scl<='0';
when 8=>cnt1:=cnt1-1;
count1:=0;
if cnt1=0 then
cnt1:=8;
R_current_state<=R_check_ack5;
FLAG<='1';
else R_current_state<=R_read_data2;
end if;
when others=>null;
end case;
when R_check_ack5=>count1:=count1+1; --查询应答信号
case count1 is
when 1 =>sda<='0';
when 3 =>scl<='1';
when 7 =>scl<='0';
when 8 =>R_current_state<=R_read_data3;
count1:=0;
when others=>null;
end case;
when R_read_data3=>count1:=count1+1;FLAG<='0'; --读操作
case count1 is
when 1=>sda<='Z';
when 3=>scl<='1';
when 5=>RTC_HOR(cnt1)<=sda;
when 7=>scl<='0';
when 8=>cnt1:=cnt1-1;
count1:=0;
if cnt1=0 then
cnt1:=8;
R_current_state<=R_check_ack6;
FLAG<='1';
else R_current_state<=R_read_data3;
end if;
when others=>null;
end case;
when R_check_ack6=>count1:=count1+1; --查询应答信号
case count1 is
when 1 =>sda<='0';
when 3 =>scl<='1';
when 7 =>scl<='0';
when 8 =>R_current_state<=R_read_data4;
count1:=0;
when others=>null;
end case;
when R_read_data4=>count1:=count1+1;FLAG<='0'; --读操作
case count1 is
when 1=>sda<='Z';
when 3=>scl<='1';
when 5=>RTC_DAY(cnt1)<=sda;
when 7=>scl<='0';
when 8=>cnt1:=cnt1-1;
count1:=0;
if cnt1=0 then
cnt1:=8;
R_current_state<=R_check_ack7;
FLAG<='1';
else R_current_state<=R_read_data4;
end if;
when others=>null;
end case;
when R_check_ack7=>count1:=count1+1; --查询应答信号
case count1 is
when 1 =>sda<='0';
when 3 =>scl<='1';
when 7 =>scl<='0';
when 8 =>R_current_state<=R_read_data5;
count1:=0;
when others=>null;
end case;
when R_read_data5=>count1:=count1+1;FLAG<='0'; --读操作
case count1 is
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