me_tb.vhd

曼彻斯特编码的VHDL源程序?顾固乇嗦氲腣HDL源程序

--  Manchester encoder test bench

-- lester sanders

library ieee ;
use ieee.std_logic_1164.all ;

entity testbench is end ;

architecture v1 of testbench is 

component me

port (rst : in std_logic ;
	clk : in std_logic ;
	wr : in std_logic ;
	din : in std_logic_vector (7 downto 0);
	ready : out std_logic ;
	mdo : out std_logic 
	);

end component ;

signal rst : std_logic ;
signal clk : std_logic ;
signal wr : std_logic ;
signal din : std_logic_vector (7 downto 0) ;
signal ready : std_logic ;
signal mdo : std_logic ;

type test_record is record

rst : std_logic ;
wr : std_logic ;
din : std_logic_vector (7 downto 0) ;
ready : std_logic ;
mdo : std_logic ;

end record ;

type test_array is array(positive range<>) of test_record ;

constant test_vectors : test_array := (

('1','0',"00000000",'0','0'), -- 40
('0','0',"10101010",'0','0'), -- 80
('0','1',"10101010",'0','0'), -- 120
('0','0',"10101010",'0','0'), -- 160
('0','0',"10101010",'0','0'), -- 200
('0','0',"10101010",'0','0'), -- 240
('0','0',"10101010",'0','0'), -- 280
('0','0',"10101010",'0','0'), -- 320
('0','0',"10101010",'0','0'), -- 360
('0','0',"10101010",'0','0'), -- 400
('0','0',"10101010",'0','0'), -- 440
('0','0',"10101010",'0','0'), -- 480
('0','0',"10101010",'0','0'), -- 520
('0','0',"10101010",'0','0'), -- 560
('0','1',"11111111",'0','0'), -- 600
('0','0',"11111111",'0','0'), -- 640
('0','0',"11111111",'0','0'), -- 680
('0','0',"11111111",'0','0'), -- 680
('0','0',"11111111",'0','0'), -- 720
('0','0',"11111111",'0','0'), -- 760
('0','0',"11111111",'0','0'), -- 800
('0','0',"11111111",'0','0'), -- 840
('0','0',"11111111",'0','0'), -- 880
('0','0',"11111111",'0','0'), -- 920
('0','0',"11111111",'0','0')
	) ;

begin

uut : me port map (rst,clk,wr,din,ready,mdo) ;

process
	variable vector : test_record ;
begin

	for index in test_vectors'range loop
	vector := test_vectors(index);

	rst <= vector.rst ;
	wr <= vector.wr ;
	din <= vector.din ;
	ready <= vector.ready ;
	mdo <= vector.mdo ;
	
	clk <= '0' ;
	wait for 20 ns ;
	clk <= '1' ;
	wait for 20 ns ;
	clk <= '0' ;

assert ready = test_vectors(index).ready report "Output ready is incorrect." severity note ;
assert mdo = test_vectors(index).mdo report "Output mdo is incorrect." severity note ;

end loop ;
wait ;
	
end process ;

end ;