de2_tv.map.qmsg

本源码是用verilog编写控制LCD——使用Quartusii

{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|DE2_LCD\|LCD_TEST:u1\|mLCD_ST " "Info: Selected Auto state machine encoding method for state machine \"\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST " "Info: Encoding result for state machine \"\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LCD_TEST:u1\|mLCD_ST.000011 " "Info: Encoded state bit \"LCD_TEST:u1\|mLCD_ST.000011\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LCD_TEST:u1\|mLCD_ST.000001 " "Info: Encoded state bit \"LCD_TEST:u1\|mLCD_ST.000001\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LCD_TEST:u1\|mLCD_ST.000010 " "Info: Encoded state bit \"LCD_TEST:u1\|mLCD_ST.000010\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LCD_TEST:u1\|mLCD_ST.000000 " "Info: Encoded state bit \"LCD_TEST:u1\|mLCD_ST.000000\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST.000000 0000 " "Info: State \"\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST.000000\" uses code string \"0000\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST.000010 0011 " "Info: State \"\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST.000010\" uses code string \"0011\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST.000001 0101 " "Info: State \"\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST.000001\" uses code string \"0101\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST.000011 1001 " "Info: State \"\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST.000011\" uses code string \"1001\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST " "Info: Selected Auto state machine encoding method for state machine \"\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST\"" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST " "Info: Encoding result for state machine \"\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LCD_TEST:u1\|LCD_Controller:u0\|ST.11 " "Info: Encoded state bit \"LCD_TEST:u1\|LCD_Controller:u0\|ST.11\"" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LCD_TEST:u1\|LCD_Controller:u0\|ST.01 " "Info: Encoded state bit \"LCD_TEST:u1\|LCD_Controller:u0\|ST.01\"" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LCD_TEST:u1\|LCD_Controller:u0\|ST.10 " "Info: Encoded state bit \"LCD_TEST:u1\|LCD_Controller:u0\|ST.10\"" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "LCD_TEST:u1\|LCD_Controller:u0\|ST.00 " "Info: Encoded state bit \"LCD_TEST:u1\|LCD_Controller:u0\|ST.00\"" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST.00 0000 " "Info: State \"\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST.00\" uses code string \"0000\"" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST.10 0011 " "Info: State \"\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST.10\" uses code string \"0011\"" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST.01 0101 " "Info: State \"\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST.01\" uses code string \"0101\"" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST.11 1001 " "Info: State \"\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST.11\" uses code string \"1001\"" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4 " "Warning: Hierarchy name \"TV_to_VGA:u4\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4\|itu_r656_decoder:U1 " "Warning: Hierarchy name \"TV_to_VGA:u4\|itu_r656_decoder:U1\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CBB " "Warning: Hierarchy name \"TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CBB\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CBB\|RAM2:u " "Warning: Hierarchy name \"TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CBB\|RAM2:u\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CBB\|RAM2:u\|altsyncram:altsyncram_component " "Warning: Hierarchy name \"TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CBB\|RAM2:u\|altsyncram:altsyncram_component\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CRR " "Warning: Hierarchy name \"TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CRR\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CRR\|RAM2:u " "Warning: Hierarchy name \"TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CRR\|RAM2:u\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CRR\|RAM2:u\|altsyncram:altsyncram_component " "Warning: Hierarchy name \"TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:CRR\|RAM2:u\|altsyncram:altsyncram_component\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:YYYR " "Warning: Hierarchy name \"TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:YYYR\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:YYYR\|RAM2:u " "Warning: Hierarchy name \"TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:YYYR\|RAM2:u\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:YYYR\|RAM2:u\|altsyncram:altsyncram_component " "Warning: Hierarchy name \"TV_to_VGA:u4\|itu_r656_decoder:U1\|dul_port_c1024:YYYR\|RAM2:u\|altsyncram:altsyncram_component\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[0\]~7 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA\[0\]~7 that it feeds" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[1\]~6 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA\[1\]~6 that it feeds" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[2\]~5 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA\[2\]~5 that it feeds" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[3\]~4 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA\[3\]~4 that it feeds" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[4\]~3 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA\[4\]~3 that it feeds" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0}