de2_tv.map.qmsg

本源码是用verilog编写控制LCD——使用Quartusii

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 SEG7_LUT_8:u0 " "Info: Elaborating entity \"SEG7_LUT_8\" for hierarchy \"SEG7_LUT_8:u0\"" {  } { { "DE2_TV.v" "u0" { Text "F:/DE2_TV/DE2_TV.v" 66 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT SEG7_LUT_8:u0\|SEG7_LUT:u0 " "Info: Elaborating entity \"SEG7_LUT\" for hierarchy \"SEG7_LUT_8:u0\|SEG7_LUT:u0\"" {  } { { "SEG7_LUT_8.v" "u0" { Text "F:/DE2_TV/SEG7_LUT_8.v" 5 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LCD_TEST LCD_TEST:u1 " "Info: Elaborating entity \"LCD_TEST\" for hierarchy \"LCD_TEST:u1\"" {  } { { "DE2_TV.v" "u1" { Text "F:/DE2_TV/DE2_TV.v" 75 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 LCD_TEST.v(57) " "Warning (10230): Verilog HDL assignment warning at LCD_TEST.v(57): truncated value with size 32 to match size of target (18)" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 LCD_TEST.v(65) " "Warning (10230): Verilog HDL assignment warning at LCD_TEST.v(65): truncated value with size 32 to match size of target (6)" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "LCD_TEST.v(75) " "Warning (10270): Verilog HDL statement warning at LCD_TEST.v(75): incomplete Case Statement has no default case item" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "LUT_DATA LCD_TEST.v(119) " "Warning (10240): Verilog HDL Always Construct warning at LCD_TEST.v(119): inferring latch(es) for variable \"LUT_DATA\", which holds its previous value in one or more paths through the always construct" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 119 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LUT_DATA\[8\] LCD_TEST.v(75) " "Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for \"LUT_DATA\[8\]\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LUT_DATA\[7\] LCD_TEST.v(75) " "Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for \"LUT_DATA\[7\]\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LUT_DATA\[6\] LCD_TEST.v(75) " "Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for \"LUT_DATA\[6\]\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LUT_DATA\[5\] LCD_TEST.v(75) " "Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for \"LUT_DATA\[5\]\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LUT_DATA\[4\] LCD_TEST.v(75) " "Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for \"LUT_DATA\[4\]\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LUT_DATA\[3\] LCD_TEST.v(75) " "Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for \"LUT_DATA\[3\]\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LUT_DATA\[2\] LCD_TEST.v(75) " "Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for \"LUT_DATA\[2\]\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LUT_DATA\[1\] LCD_TEST.v(75) " "Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for \"LUT_DATA\[1\]\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LUT_DATA\[0\] LCD_TEST.v(75) " "Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for \"LUT_DATA\[0\]\"" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LCD_Controller LCD_TEST:u1\|LCD_Controller:u0 " "Info: Elaborating entity \"LCD_Controller\" for hierarchy \"LCD_TEST:u1\|LCD_Controller:u0\"" {  } { { "LCD_TEST.v" "u0" { Text "F:/DE2_TV/LCD_TEST.v" 132 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 LCD_Controller.v(66) " "Warning (10230): Verilog HDL assignment warning at LCD_Controller.v(66): truncated value with size 32 to match size of target (5)" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST 4 " "Info: State machine \"\|DE2_LCD\|LCD_TEST:u1\|mLCD_ST\" contains 4 states" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 13 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST 4 " "Info: State machine \"\|DE2_LCD\|LCD_TEST:u1\|LCD_Controller:u0\|ST\" contains 4 states" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 25 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}