de2_tv.map.qmsg

本源码是用verilog编写控制LCD——使用Quartusii

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 01 20:08:27 2008 " "Info: Processing started: Tue Jul 01 20:08:27 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE2_TV -c DE2_TV " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_TV -c DE2_TV" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/DE2_TV/AUDIO_DAC.v " "Warning: Can't analyze file -- file F:/DE2_TV/AUDIO_DAC.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "DE2_LCD DE2_TV.v(29) " "Warning (10238): Verilog Module Declaration warning at DE2_TV.v(29): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"DE2_LCD\"" {  } { { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 29 0 0 } }  } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DE2_TV.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DE2_TV.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_LCD " "Info: Found entity 1: DE2_LCD" {  } { { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/DE2_TV/dul_port_c1024.v " "Warning: Can't analyze file -- file F:/DE2_TV/dul_port_c1024.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/DE2_TV/I2C_AV_Config.v " "Warning: Can't analyze file -- file F:/DE2_TV/I2C_AV_Config.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/DE2_TV/I2C_Controller.v " "Warning: Can't analyze file -- file F:/DE2_TV/I2C_Controller.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/DE2_TV/itu_r656_decoder.v " "Warning: Can't analyze file -- file F:/DE2_TV/itu_r656_decoder.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_Controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_Controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_Controller " "Info: Found entity 1: LCD_Controller" {  } { { "LCD_Controller.v" "" { Text "F:/DE2_TV/LCD_Controller.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_TEST.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_TEST.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_TEST " "Info: Found entity 1: LCD_TEST" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/DE2_TV/MAC_3.v " "Warning: Can't analyze file -- file F:/DE2_TV/MAC_3.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/DE2_TV/ram2.v " "Warning: Can't analyze file -- file F:/DE2_TV/ram2.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Info: Found entity 1: SEG7_LUT" {  } { { "SEG7_LUT.v" "" { Text "F:/DE2_TV/SEG7_LUT.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_8 " "Info: Found entity 1: SEG7_LUT_8" {  } { { "SEG7_LUT_8.v" "" { Text "F:/DE2_TV/SEG7_LUT_8.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/DE2_TV/TV_to_VGA.v " "Warning: Can't analyze file -- file F:/DE2_TV/TV_to_VGA.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/DE2_TV/VGA_Audio_PLL.v " "Warning: Can't analyze file -- file F:/DE2_TV/VGA_Audio_PLL.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/DE2_TV/YCbCr2RGB.v " "Warning: Can't analyze file -- file F:/DE2_TV/YCbCr2RGB.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DE2_LCD " "Info: Elaborating entity \"DE2_LCD\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}