📄 de2_tv.tan.qmsg
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{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "LCD_TEST:u1\|LUT_INDEX\[5\] LCD_TEST:u1\|LUT_DATA\[3\] OSC_50 3.303 ns " "Info: Found hold time violation between source pin or register \"LCD_TEST:u1\|LUT_INDEX\[5\]\" and destination pin or register \"LCD_TEST:u1\|LUT_DATA\[3\]\" for clock \"OSC_50\" (Hold time is 3.303 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.917 ns + Largest " "Info: + Largest clock skew is 5.917 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC_50 destination 9.087 ns + Longest register " "Info: + Longest clock path from clock \"OSC_50\" to destination register is 9.087 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns OSC_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'OSC_50'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OSC_50 } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns OSC_50~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'OSC_50~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.239 ns" { OSC_50 OSC_50~clkctrl } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(0.970 ns) 3.474 ns LCD_TEST:u1\|LUT_INDEX\[3\] 3 REG LCFF_X1_Y27_N7 21 " "Info: 3: + IC(1.155 ns) + CELL(0.970 ns) = 3.474 ns; Loc. = LCFF_X1_Y27_N7; Fanout = 21; REG Node = 'LCD_TEST:u1\|LUT_INDEX\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.125 ns" { OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.506 ns) + CELL(0.651 ns) 4.631 ns LCD_TEST:u1\|WideOr0~49 4 COMB LCCOMB_X1_Y27_N20 1 " "Info: 4: + IC(0.506 ns) + CELL(0.651 ns) = 4.631 ns; Loc. = LCCOMB_X1_Y27_N20; Fanout = 1; COMB Node = 'LCD_TEST:u1\|WideOr0~49'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.157 ns" { LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.366 ns) 5.367 ns LCD_TEST:u1\|WideOr0~50 5 COMB LCCOMB_X1_Y27_N24 1 " "Info: 5: + IC(0.370 ns) + CELL(0.366 ns) = 5.367 ns; Loc. = LCCOMB_X1_Y27_N24; Fanout = 1; COMB Node = 'LCD_TEST:u1\|WideOr0~50'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.736 ns" { LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.865 ns) + CELL(0.000 ns) 7.232 ns LCD_TEST:u1\|WideOr0~50clkctrl 6 COMB CLKCTRL_G1 9 " "Info: 6: + IC(1.865 ns) + CELL(0.000 ns) = 7.232 ns; Loc. = CLKCTRL_G1; Fanout = 9; COMB Node = 'LCD_TEST:u1\|WideOr0~50clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.865 ns" { LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.649 ns) + CELL(0.206 ns) 9.087 ns LCD_TEST:u1\|LUT_DATA\[3\] 7 REG LCCOMB_X3_Y27_N18 1 " "Info: 7: + IC(1.649 ns) + CELL(0.206 ns) = 9.087 ns; Loc. = LCCOMB_X3_Y27_N18; Fanout = 1; REG Node = 'LCD_TEST:u1\|LUT_DATA\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.855 ns" { LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[3] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.303 ns ( 36.35 % ) " "Info: Total cell delay = 3.303 ns ( 36.35 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.784 ns ( 63.65 % ) " "Info: Total interconnect delay = 5.784 ns ( 63.65 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.087 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.087 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[3] } { 0.000ns 0.000ns 0.239ns 1.155ns 0.506ns 0.370ns 1.865ns 1.649ns } { 0.000ns 1.110ns 0.000ns 0.970ns 0.651ns 0.366ns 0.000ns 0.206ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC_50 source 3.170 ns - Shortest register " "Info: - Shortest clock path from clock \"OSC_50\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns OSC_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'OSC_50'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OSC_50 } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns OSC_50~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'OSC_50~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.239 ns" { OSC_50 OSC_50~clkctrl } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(0.666 ns) 3.170 ns LCD_TEST:u1\|LUT_INDEX\[5\] 3 REG LCFF_X1_Y27_N11 16 " "Info: 3: + IC(1.155 ns) + CELL(0.666 ns) = 3.170 ns; Loc. = LCFF_X1_Y27_N11; Fanout = 16; REG Node = 'LCD_TEST:u1\|LUT_INDEX\[5\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.821 ns" { OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[5] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 56.03 % ) " "Info: Total cell delay = 1.776 ns ( 56.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.394 ns ( 43.97 % ) " "Info: Total interconnect delay = 1.394 ns ( 43.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[5] } { 0.000ns 0.000ns 0.239ns 1.155ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.087 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.087 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[3] } { 0.000ns 0.000ns 0.239ns 1.155ns 0.506ns 0.370ns 1.865ns 1.649ns } { 0.000ns 1.110ns 0.000ns 0.970ns 0.651ns 0.366ns 0.000ns 0.206ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[5] } { 0.000ns 0.000ns 0.239ns 1.155ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" { } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.310 ns - Shortest register register " "Info: - Shortest register to register delay is 2.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_TEST:u1\|LUT_INDEX\[5\] 1 REG LCFF_X1_Y27_N11 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y27_N11; Fanout = 16; REG Node = 'LCD_TEST:u1\|LUT_INDEX\[5\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_TEST:u1|LUT_INDEX[5] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.206 ns) + CELL(0.366 ns) 1.572 ns LCD_TEST:u1\|WideOr11~199 2 COMB LCCOMB_X3_Y27_N20 1 " "Info: 2: + IC(1.206 ns) + CELL(0.366 ns) = 1.572 ns; Loc. = LCCOMB_X3_Y27_N20; Fanout = 1; COMB Node = 'LCD_TEST:u1\|WideOr11~199'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.572 ns" { LCD_TEST:u1|LUT_INDEX[5] LCD_TEST:u1|WideOr11~199 } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.370 ns) 2.310 ns LCD_TEST:u1\|LUT_DATA\[3\] 3 REG LCCOMB_X3_Y27_N18 1 " "Info: 3: + IC(0.368 ns) + CELL(0.370 ns) = 2.310 ns; Loc. = LCCOMB_X3_Y27_N18; Fanout = 1; REG Node = 'LCD_TEST:u1\|LUT_DATA\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.738 ns" { LCD_TEST:u1|WideOr11~199 LCD_TEST:u1|LUT_DATA[3] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.736 ns ( 31.86 % ) " "Info: Total cell delay = 0.736 ns ( 31.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.574 ns ( 68.14 % ) " "Info: Total interconnect delay = 1.574 ns ( 68.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.310 ns" { LCD_TEST:u1|LUT_INDEX[5] LCD_TEST:u1|WideOr11~199 LCD_TEST:u1|LUT_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.310 ns" { LCD_TEST:u1|LUT_INDEX[5] LCD_TEST:u1|WideOr11~199 LCD_TEST:u1|LUT_DATA[3] } { 0.000ns 1.206ns 0.368ns } { 0.000ns 0.366ns 0.370ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" { } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.087 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.087 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[3] } { 0.000ns 0.000ns 0.239ns 1.155ns 0.506ns 0.370ns 1.865ns 1.649ns } { 0.000ns 1.110ns 0.000ns 0.970ns 0.651ns 0.366ns 0.000ns 0.206ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[5] } { 0.000ns 0.000ns 0.239ns 1.155ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.310 ns" { LCD_TEST:u1|LUT_INDEX[5] LCD_TEST:u1|WideOr11~199 LCD_TEST:u1|LUT_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.310 ns" { LCD_TEST:u1|LUT_INDEX[5] LCD_TEST:u1|WideOr11~199 LCD_TEST:u1|LUT_DATA[3] } { 0.000ns 1.206ns 0.368ns } { 0.000ns 0.366ns 0.370ns } } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "OSC_50 LCD_DATA\[6\] LCD_TEST:u1\|mLCD_DATA\[6\] 8.004 ns register " "Info: tco from clock \"OSC_50\" to destination pin \"LCD_DATA\[6\]\" through register \"LCD_TEST:u1\|mLCD_DATA\[6\]\" is 8.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC_50 source 3.183 ns + Longest register " "Info: + Longest clock path from clock \"OSC_50\" to source register is 3.183 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns OSC_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'OSC_50'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OSC_50 } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns OSC_50~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'OSC_50~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.239 ns" { OSC_50 OSC_50~clkctrl } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.168 ns) + CELL(0.666 ns) 3.183 ns LCD_TEST:u1\|mLCD_DATA\[6\] 3 REG LCFF_X4_Y28_N1 1 " "Info: 3: + IC(1.168 ns) + CELL(0.666 ns) = 3.183 ns; Loc. = LCFF_X4_Y28_N1; Fanout = 1; REG Node = 'LCD_TEST:u1\|mLCD_DATA\[6\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.834 ns" { OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[6] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.80 % ) " "Info: Total cell delay = 1.776 ns ( 55.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.407 ns ( 44.20 % ) " "Info: Total interconnect delay = 1.407 ns ( 44.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.183 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.183 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[6] } { 0.000ns 0.000ns 0.239ns 1.168ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.517 ns + Longest register pin " "Info: + Longest register to pin delay is 4.517 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_TEST:u1\|mLCD_DATA\[6\] 1 REG LCFF_X4_Y28_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y28_N1; Fanout = 1; REG Node = 'LCD_TEST:u1\|mLCD_DATA\[6\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_TEST:u1|mLCD_DATA[6] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(3.066 ns) 4.517 ns LCD_DATA\[6\] 2 PIN PIN_H4 0 " "Info: 2: + IC(1.451 ns) + CELL(3.066 ns) = 4.517 ns; Loc. = PIN_H4; Fanout = 0; PIN Node = 'LCD_DATA\[6\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.517 ns" { LCD_TEST:u1|mLCD_DATA[6] LCD_DATA[6] } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 51 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.066 ns ( 67.88 % ) " "Info: Total cell delay = 3.066 ns ( 67.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.451 ns ( 32.12 % ) " "Info: Total interconnect delay = 1.451 ns ( 32.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.517 ns" { LCD_TEST:u1|mLCD_DATA[6] LCD_DATA[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.517 ns" { LCD_TEST:u1|mLCD_DATA[6] LCD_DATA[6] } { 0.000ns 1.451ns } { 0.000ns 3.066ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.183 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.183 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[6] } { 0.000ns 0.000ns 0.239ns 1.168ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.517 ns" { LCD_TEST:u1|mLCD_DATA[6] LCD_DATA[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.517 ns" { LCD_TEST:u1|mLCD_DATA[6] LCD_DATA[6] } { 0.000ns 1.451ns } { 0.000ns 3.066ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 13 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 01 20:09:44 2008 " "Info: Processing ended: Tue Jul 01 20:09:44 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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