de2_tv.tan.qmsg

本源码是用verilog编写控制LCD——使用Quartusii

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "OSC_50 " "Info: Assuming node \"OSC_50\" is an undefined clock" {  } { { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OSC_50" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "LCD_TEST:u1\|WideOr0~49 " "Info: Detected gated clock \"LCD_TEST:u1\|WideOr0~49\" as buffer" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_TEST:u1\|WideOr0~49" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LCD_TEST:u1\|WideOr0~50 " "Info: Detected gated clock \"LCD_TEST:u1\|WideOr0~50\" as buffer" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_TEST:u1\|WideOr0~50" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "LCD_TEST:u1\|LUT_INDEX\[3\] " "Info: Detected ripple clock \"LCD_TEST:u1\|LUT_INDEX\[3\]\" as buffer" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_TEST:u1\|LUT_INDEX\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "LCD_TEST:u1\|LUT_INDEX\[4\] " "Info: Detected ripple clock \"LCD_TEST:u1\|LUT_INDEX\[4\]\" as buffer" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_TEST:u1\|LUT_INDEX\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "LCD_TEST:u1\|LUT_INDEX\[2\] " "Info: Detected ripple clock \"LCD_TEST:u1\|LUT_INDEX\[2\]\" as buffer" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_TEST:u1\|LUT_INDEX\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "LCD_TEST:u1\|LUT_INDEX\[1\] " "Info: Detected ripple clock \"LCD_TEST:u1\|LUT_INDEX\[1\]\" as buffer" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_TEST:u1\|LUT_INDEX\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "LCD_TEST:u1\|LUT_INDEX\[5\] " "Info: Detected ripple clock \"LCD_TEST:u1\|LUT_INDEX\[5\]\" as buffer" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_TEST:u1\|LUT_INDEX\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "OSC_50 register LCD_TEST:u1\|LUT_DATA\[4\] register LCD_TEST:u1\|mLCD_DATA\[4\] 165.54 MHz 6.041 ns Internal " "Info: Clock \"OSC_50\" has Internal fmax of 165.54 MHz between source register \"LCD_TEST:u1\|LUT_DATA\[4\]\" and destination register \"LCD_TEST:u1\|mLCD_DATA\[4\]\" (period= 6.041 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.108 ns + Longest register register " "Info: + Longest register to register delay is 0.108 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_TEST:u1\|LUT_DATA\[4\] 1 REG LCCOMB_X1_Y28_N14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X1_Y28_N14; Fanout = 1; REG Node = 'LCD_TEST:u1\|LUT_DATA\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_TEST:u1|LUT_DATA[4] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.108 ns LCD_TEST:u1\|mLCD_DATA\[4\] 2 REG LCFF_X1_Y28_N15 1 " "Info: 2: + IC(0.000 ns) + CELL(0.108 ns) = 0.108 ns; Loc. = LCFF_X1_Y28_N15; Fanout = 1; REG Node = 'LCD_TEST:u1\|mLCD_DATA\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { LCD_TEST:u1|LUT_DATA[4] LCD_TEST:u1|mLCD_DATA[4] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.108 ns ( 100.00 % ) " "Info: Total cell delay = 0.108 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { LCD_TEST:u1|LUT_DATA[4] LCD_TEST:u1|mLCD_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.108 ns" { LCD_TEST:u1|LUT_DATA[4] LCD_TEST:u1|mLCD_DATA[4] } { 0.000ns 0.000ns } { 0.000ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.973 ns - Smallest " "Info: - Smallest clock skew is -5.973 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC_50 destination 3.179 ns + Shortest register " "Info: + Shortest clock path from clock \"OSC_50\" to destination register is 3.179 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns OSC_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'OSC_50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OSC_50 } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns OSC_50~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'OSC_50~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.239 ns" { OSC_50 OSC_50~clkctrl } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.164 ns) + CELL(0.666 ns) 3.179 ns LCD_TEST:u1\|mLCD_DATA\[4\] 3 REG LCFF_X1_Y28_N15 1 " "Info: 3: + IC(1.164 ns) + CELL(0.666 ns) = 3.179 ns; Loc. = LCFF_X1_Y28_N15; Fanout = 1; REG Node = 'LCD_TEST:u1\|mLCD_DATA\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.830 ns" { OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[4] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.87 % ) " "Info: Total cell delay = 1.776 ns ( 55.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.403 ns ( 44.13 % ) " "Info: Total interconnect delay = 1.403 ns ( 44.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.179 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.179 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[4] } { 0.000ns 0.000ns 0.239ns 1.164ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "OSC_50 source 9.152 ns - Longest register " "Info: - Longest clock path from clock \"OSC_50\" to source register is 9.152 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns OSC_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'OSC_50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OSC_50 } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns OSC_50~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'OSC_50~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.239 ns" { OSC_50 OSC_50~clkctrl } "NODE_NAME" } } { "DE2_TV.v" "" { Text "F:/DE2_TV/DE2_TV.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(0.970 ns) 3.474 ns LCD_TEST:u1\|LUT_INDEX\[3\] 3 REG LCFF_X1_Y27_N7 21 " "Info: 3: + IC(1.155 ns) + CELL(0.970 ns) = 3.474 ns; Loc. = LCFF_X1_Y27_N7; Fanout = 21; REG Node = 'LCD_TEST:u1\|LUT_INDEX\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.125 ns" { OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.506 ns) + CELL(0.651 ns) 4.631 ns LCD_TEST:u1\|WideOr0~49 4 COMB LCCOMB_X1_Y27_N20 1 " "Info: 4: + IC(0.506 ns) + CELL(0.651 ns) = 4.631 ns; Loc. = LCCOMB_X1_Y27_N20; Fanout = 1; COMB Node = 'LCD_TEST:u1\|WideOr0~49'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.157 ns" { LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.366 ns) 5.367 ns LCD_TEST:u1\|WideOr0~50 5 COMB LCCOMB_X1_Y27_N24 1 " "Info: 5: + IC(0.370 ns) + CELL(0.366 ns) = 5.367 ns; Loc. = LCCOMB_X1_Y27_N24; Fanout = 1; COMB Node = 'LCD_TEST:u1\|WideOr0~50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.736 ns" { LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.865 ns) + CELL(0.000 ns) 7.232 ns LCD_TEST:u1\|WideOr0~50clkctrl 6 COMB CLKCTRL_G1 9 " "Info: 6: + IC(1.865 ns) + CELL(0.000 ns) = 7.232 ns; Loc. = CLKCTRL_G1; Fanout = 9; COMB Node = 'LCD_TEST:u1\|WideOr0~50clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.865 ns" { LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.714 ns) + CELL(0.206 ns) 9.152 ns LCD_TEST:u1\|LUT_DATA\[4\] 7 REG LCCOMB_X1_Y28_N14 1 " "Info: 7: + IC(1.714 ns) + CELL(0.206 ns) = 9.152 ns; Loc. = LCCOMB_X1_Y28_N14; Fanout = 1; REG Node = 'LCD_TEST:u1\|LUT_DATA\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.920 ns" { LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[4] } "NODE_NAME" } } { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.303 ns ( 36.09 % ) " "Info: Total cell delay = 3.303 ns ( 36.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.849 ns ( 63.91 % ) " "Info: Total interconnect delay = 5.849 ns ( 63.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.152 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.152 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[4] } { 0.000ns 0.000ns 0.239ns 1.155ns 0.506ns 0.370ns 1.865ns 1.714ns } { 0.000ns 1.110ns 0.000ns 0.970ns 0.651ns 0.366ns 0.000ns 0.206ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.179 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.179 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[4] } { 0.000ns 0.000ns 0.239ns 1.164ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.152 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.152 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[4] } { 0.000ns 0.000ns 0.239ns 1.155ns 0.506ns 0.370ns 1.865ns 1.714ns } { 0.000ns 1.110ns 0.000ns 0.970ns 0.651ns 0.366ns 0.000ns 0.206ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 75 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "LCD_TEST.v" "" { Text "F:/DE2_TV/LCD_TEST.v" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { LCD_TEST:u1|LUT_DATA[4] LCD_TEST:u1|mLCD_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.108 ns" { LCD_TEST:u1|LUT_DATA[4] LCD_TEST:u1|mLCD_DATA[4] } { 0.000ns 0.000ns } { 0.000ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.179 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.179 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|mLCD_DATA[4] } { 0.000ns 0.000ns 0.239ns 1.164ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.152 ns" { OSC_50 OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.152 ns" { OSC_50 OSC_50~combout OSC_50~clkctrl LCD_TEST:u1|LUT_INDEX[3] LCD_TEST:u1|WideOr0~49 LCD_TEST:u1|WideOr0~50 LCD_TEST:u1|WideOr0~50clkctrl LCD_TEST:u1|LUT_DATA[4] } { 0.000ns 0.000ns 0.239ns 1.155ns 0.506ns 0.370ns 1.865ns 1.714ns } { 0.000ns 1.110ns 0.000ns 0.970ns 0.651ns 0.366ns 0.000ns 0.206ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "OSC_50 54 " "Warning: Circuit may not operate. Detected 54 non-operational path(s) clocked by clock \"OSC_50\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}