de2_tv.hier_info

本源码是用verilog编写控制LCD——使用Quartusii

|DE2_LCD
OSC_50 => OSC_50~0.IN1
KEY[0] => DLY_RST.IN1
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
HEX0[0] <= SEG7_LUT_8:u0.port0
HEX0[1] <= SEG7_LUT_8:u0.port0
HEX0[2] <= SEG7_LUT_8:u0.port0
HEX0[3] <= SEG7_LUT_8:u0.port0
HEX0[4] <= SEG7_LUT_8:u0.port0
HEX0[5] <= SEG7_LUT_8:u0.port0
HEX0[6] <= SEG7_LUT_8:u0.port0
HEX1[0] <= SEG7_LUT_8:u0.port1
HEX1[1] <= SEG7_LUT_8:u0.port1
HEX1[2] <= SEG7_LUT_8:u0.port1
HEX1[3] <= SEG7_LUT_8:u0.port1
HEX1[4] <= SEG7_LUT_8:u0.port1
HEX1[5] <= SEG7_LUT_8:u0.port1
HEX1[6] <= SEG7_LUT_8:u0.port1
HEX2[0] <= SEG7_LUT_8:u0.port2
HEX2[1] <= SEG7_LUT_8:u0.port2
HEX2[2] <= SEG7_LUT_8:u0.port2
HEX2[3] <= SEG7_LUT_8:u0.port2
HEX2[4] <= SEG7_LUT_8:u0.port2
HEX2[5] <= SEG7_LUT_8:u0.port2
HEX2[6] <= SEG7_LUT_8:u0.port2
HEX3[0] <= SEG7_LUT_8:u0.port3
HEX3[1] <= SEG7_LUT_8:u0.port3
HEX3[2] <= SEG7_LUT_8:u0.port3
HEX3[3] <= SEG7_LUT_8:u0.port3
HEX3[4] <= SEG7_LUT_8:u0.port3
HEX3[5] <= SEG7_LUT_8:u0.port3
HEX3[6] <= SEG7_LUT_8:u0.port3
HEX4[0] <= SEG7_LUT_8:u0.port4
HEX4[1] <= SEG7_LUT_8:u0.port4
HEX4[2] <= SEG7_LUT_8:u0.port4
HEX4[3] <= SEG7_LUT_8:u0.port4
HEX4[4] <= SEG7_LUT_8:u0.port4
HEX4[5] <= SEG7_LUT_8:u0.port4
HEX4[6] <= SEG7_LUT_8:u0.port4
HEX5[0] <= SEG7_LUT_8:u0.port5
HEX5[1] <= SEG7_LUT_8:u0.port5
HEX5[2] <= SEG7_LUT_8:u0.port5
HEX5[3] <= SEG7_LUT_8:u0.port5
HEX5[4] <= SEG7_LUT_8:u0.port5
HEX5[5] <= SEG7_LUT_8:u0.port5
HEX5[6] <= SEG7_LUT_8:u0.port5
HEX6[0] <= SEG7_LUT_8:u0.port6
HEX6[1] <= SEG7_LUT_8:u0.port6
HEX6[2] <= SEG7_LUT_8:u0.port6
HEX6[3] <= SEG7_LUT_8:u0.port6
HEX6[4] <= SEG7_LUT_8:u0.port6
HEX6[5] <= SEG7_LUT_8:u0.port6
HEX6[6] <= SEG7_LUT_8:u0.port6
HEX7[0] <= SEG7_LUT_8:u0.port7
HEX7[1] <= SEG7_LUT_8:u0.port7
HEX7[2] <= SEG7_LUT_8:u0.port7
HEX7[3] <= SEG7_LUT_8:u0.port7
HEX7[4] <= SEG7_LUT_8:u0.port7
HEX7[5] <= SEG7_LUT_8:u0.port7
HEX7[6] <= SEG7_LUT_8:u0.port7
LED_GREEN[0] <= <VCC>
LED_GREEN[1] <= <VCC>
LED_GREEN[2] <= <VCC>
LED_GREEN[3] <= <VCC>
LED_GREEN[4] <= <VCC>
LED_GREEN[5] <= <VCC>
LED_GREEN[6] <= <VCC>
LED_GREEN[7] <= <VCC>
LED_GREEN[8] <= <VCC>
LED_RED[0] <= <VCC>
LED_RED[1] <= <VCC>
LED_RED[2] <= <VCC>
LED_RED[3] <= <VCC>
LED_RED[4] <= <VCC>
LED_RED[5] <= <VCC>
LED_RED[6] <= <VCC>
LED_RED[7] <= <VCC>
LED_RED[8] <= <VCC>
LED_RED[9] <= <VCC>
LED_RED[10] <= <VCC>
LED_RED[11] <= <VCC>
LED_RED[12] <= <VCC>
LED_RED[13] <= <VCC>
LED_RED[14] <= <VCC>
LED_RED[15] <= <VCC>
LED_RED[16] <= <VCC>
LED_RED[17] <= <VCC>
LCD_ON <= <VCC>
LCD_BLON <= <VCC>
LCD_RW <= LCD_TEST:u1.LCD_RW
LCD_EN <= LCD_TEST:u1.LCD_EN
LCD_RS <= LCD_TEST:u1.LCD_RS
LCD_DATA[0] <= LCD_TEST:u1.LCD_DATA
LCD_DATA[1] <= LCD_TEST:u1.LCD_DATA
LCD_DATA[2] <= LCD_TEST:u1.LCD_DATA
LCD_DATA[3] <= LCD_TEST:u1.LCD_DATA
LCD_DATA[4] <= LCD_TEST:u1.LCD_DATA
LCD_DATA[5] <= LCD_TEST:u1.LCD_DATA
LCD_DATA[6] <= LCD_TEST:u1.LCD_DATA
LCD_DATA[7] <= LCD_TEST:u1.LCD_DATA


|DE2_LCD|SEG7_LUT_8:u0
oSEG0[0] <= SEG7_LUT:u0.port0
oSEG0[1] <= SEG7_LUT:u0.port0
oSEG0[2] <= SEG7_LUT:u0.port0
oSEG0[3] <= SEG7_LUT:u0.port0
oSEG0[4] <= SEG7_LUT:u0.port0
oSEG0[5] <= SEG7_LUT:u0.port0
oSEG0[6] <= SEG7_LUT:u0.port0
oSEG1[0] <= SEG7_LUT:u1.port0
oSEG1[1] <= SEG7_LUT:u1.port0
oSEG1[2] <= SEG7_LUT:u1.port0
oSEG1[3] <= SEG7_LUT:u1.port0
oSEG1[4] <= SEG7_LUT:u1.port0
oSEG1[5] <= SEG7_LUT:u1.port0
oSEG1[6] <= SEG7_LUT:u1.port0
oSEG2[0] <= SEG7_LUT:u2.port0
oSEG2[1] <= SEG7_LUT:u2.port0
oSEG2[2] <= SEG7_LUT:u2.port0
oSEG2[3] <= SEG7_LUT:u2.port0
oSEG2[4] <= SEG7_LUT:u2.port0
oSEG2[5] <= SEG7_LUT:u2.port0
oSEG2[6] <= SEG7_LUT:u2.port0
oSEG3[0] <= SEG7_LUT:u3.port0
oSEG3[1] <= SEG7_LUT:u3.port0
oSEG3[2] <= SEG7_LUT:u3.port0
oSEG3[3] <= SEG7_LUT:u3.port0
oSEG3[4] <= SEG7_LUT:u3.port0
oSEG3[5] <= SEG7_LUT:u3.port0
oSEG3[6] <= SEG7_LUT:u3.port0
oSEG4[0] <= SEG7_LUT:u4.port0
oSEG4[1] <= SEG7_LUT:u4.port0
oSEG4[2] <= SEG7_LUT:u4.port0
oSEG4[3] <= SEG7_LUT:u4.port0
oSEG4[4] <= SEG7_LUT:u4.port0
oSEG4[5] <= SEG7_LUT:u4.port0
oSEG4[6] <= SEG7_LUT:u4.port0
oSEG5[0] <= SEG7_LUT:u5.port0
oSEG5[1] <= SEG7_LUT:u5.port0
oSEG5[2] <= SEG7_LUT:u5.port0
oSEG5[3] <= SEG7_LUT:u5.port0
oSEG5[4] <= SEG7_LUT:u5.port0
oSEG5[5] <= SEG7_LUT:u5.port0
oSEG5[6] <= SEG7_LUT:u5.port0
oSEG6[0] <= SEG7_LUT:u6.port0
oSEG6[1] <= SEG7_LUT:u6.port0
oSEG6[2] <= SEG7_LUT:u6.port0
oSEG6[3] <= SEG7_LUT:u6.port0
oSEG6[4] <= SEG7_LUT:u6.port0
oSEG6[5] <= SEG7_LUT:u6.port0
oSEG6[6] <= SEG7_LUT:u6.port0
oSEG7[0] <= SEG7_LUT:u7.port0
oSEG7[1] <= SEG7_LUT:u7.port0
oSEG7[2] <= SEG7_LUT:u7.port0
oSEG7[3] <= SEG7_LUT:u7.port0
oSEG7[4] <= SEG7_LUT:u7.port0
oSEG7[5] <= SEG7_LUT:u7.port0
oSEG7[6] <= SEG7_LUT:u7.port0
iDIG[0] => iDIG[0]~31.IN1
iDIG[1] => iDIG[1]~30.IN1
iDIG[2] => iDIG[2]~29.IN1
iDIG[3] => iDIG[3]~28.IN1
iDIG[4] => iDIG[4]~27.IN1
iDIG[5] => iDIG[5]~26.IN1
iDIG[6] => iDIG[6]~25.IN1
iDIG[7] => iDIG[7]~24.IN1
iDIG[8] => iDIG[8]~23.IN1
iDIG[9] => iDIG[9]~22.IN1
iDIG[10] => iDIG[10]~21.IN1
iDIG[11] => iDIG[11]~20.IN1
iDIG[12] => iDIG[12]~19.IN1
iDIG[13] => iDIG[13]~18.IN1
iDIG[14] => iDIG[14]~17.IN1
iDIG[15] => iDIG[15]~16.IN1
iDIG[16] => iDIG[16]~15.IN1
iDIG[17] => iDIG[17]~14.IN1
iDIG[18] => iDIG[18]~13.IN1
iDIG[19] => iDIG[19]~12.IN1
iDIG[20] => iDIG[20]~11.IN1
iDIG[21] => iDIG[21]~10.IN1
iDIG[22] => iDIG[22]~9.IN1
iDIG[23] => iDIG[23]~8.IN1
iDIG[24] => iDIG[24]~7.IN1
iDIG[25] => iDIG[25]~6.IN1
iDIG[26] => iDIG[26]~5.IN1
iDIG[27] => iDIG[27]~4.IN1
iDIG[28] => iDIG[28]~3.IN1
iDIG[29] => iDIG[29]~2.IN1
iDIG[30] => iDIG[30]~1.IN1
iDIG[31] => iDIG[31]~0.IN1


|DE2_LCD|SEG7_LUT_8:u0|SEG7_LUT:u0
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCD|SEG7_LUT_8:u0|SEG7_LUT:u1
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCD|SEG7_LUT_8:u0|SEG7_LUT:u2
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCD|SEG7_LUT_8:u0|SEG7_LUT:u3
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCD|SEG7_LUT_8:u0|SEG7_LUT:u4
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCD|SEG7_LUT_8:u0|SEG7_LUT:u5
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCD|SEG7_LUT_8:u0|SEG7_LUT:u6
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCD|SEG7_LUT_8:u0|SEG7_LUT:u7
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_LCD|LCD_TEST:u1
iCLK => iCLK~0.IN1
iRST_N => iRST_N~0.IN1
LCD_DATA[0] <= LCD_Controller:u0.LCD_DATA
LCD_DATA[1] <= LCD_Controller:u0.LCD_DATA
LCD_DATA[2] <= LCD_Controller:u0.LCD_DATA
LCD_DATA[3] <= LCD_Controller:u0.LCD_DATA
LCD_DATA[4] <= LCD_Controller:u0.LCD_DATA
LCD_DATA[5] <= LCD_Controller:u0.LCD_DATA
LCD_DATA[6] <= LCD_Controller:u0.LCD_DATA
LCD_DATA[7] <= LCD_Controller:u0.LCD_DATA
LCD_RW <= LCD_Controller:u0.LCD_RW
LCD_EN <= LCD_Controller:u0.LCD_EN
LCD_RS <= LCD_Controller:u0.LCD_RS


|DE2_LCD|LCD_TEST:u1|LCD_Controller:u0
iDATA[0] => LCD_DATA[0].DATAIN
iDATA[1] => LCD_DATA[1].DATAIN
iDATA[2] => LCD_DATA[2].DATAIN
iDATA[3] => LCD_DATA[3].DATAIN
iDATA[4] => LCD_DATA[4].DATAIN
iDATA[5] => LCD_DATA[5].DATAIN
iDATA[6] => LCD_DATA[6].DATAIN
iDATA[7] => LCD_DATA[7].DATAIN
iRS => LCD_RS.DATAIN
iStart => preStart.DATAIN
iStart => Equal0.IN0
oDone <= oDone~reg0.DB_MAX_OUTPUT_PORT_TYPE
iCLK => LCD_EN~reg0.CLK
iCLK => preStart.CLK
iCLK => mStart.CLK
iCLK => Cont[4].CLK
iCLK => Cont[3].CLK
iCLK => Cont[2].CLK
iCLK => Cont[1].CLK
iCLK => Cont[0].CLK
iCLK => oDone~reg0.CLK
iCLK => ST~11.IN1
iRST_N => LCD_EN~reg0.ACLR
iRST_N => preStart.ACLR
iRST_N => mStart.ACLR
iRST_N => Cont[4].ACLR
iRST_N => Cont[3].ACLR
iRST_N => Cont[2].ACLR
iRST_N => Cont[1].ACLR
iRST_N => Cont[0].ACLR
iRST_N => oDone~reg0.ACLR
iRST_N => ST~12.IN1
LCD_DATA[0] <= iDATA[0].DB_MAX_OUTPUT_PORT_TYPE
LCD_DATA[1] <= iDATA[1].DB_MAX_OUTPUT_PORT_TYPE
LCD_DATA[2] <= iDATA[2].DB_MAX_OUTPUT_PORT_TYPE
LCD_DATA[3] <= iDATA[3].DB_MAX_OUTPUT_PORT_TYPE
LCD_DATA[4] <= iDATA[4].DB_MAX_OUTPUT_PORT_TYPE
LCD_DATA[5] <= iDATA[5].DB_MAX_OUTPUT_PORT_TYPE
LCD_DATA[6] <= iDATA[6].DB_MAX_OUTPUT_PORT_TYPE
LCD_DATA[7] <= iDATA[7].DB_MAX_OUTPUT_PORT_TYPE
LCD_RW <= <GND>
LCD_EN <= LCD_EN~reg0.DB_MAX_OUTPUT_PORT_TYPE
LCD_RS <= iRS.DB_MAX_OUTPUT_PORT_TYPE