de2_tv.tan.summary

本源码是用verilog编写控制LCD——使用Quartusii

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.004 ns
From           : LCD_TEST:u1|mLCD_DATA[6]
To             : LCD_DATA[6]
From Clock     : OSC_50
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'OSC_50'
Slack          : N/A
Required Time  : None
Actual Time    : 165.54 MHz ( period = 6.041 ns )
From           : LCD_TEST:u1|LUT_DATA[4]
To             : LCD_TEST:u1|mLCD_DATA[4]
From Clock     : OSC_50
To Clock       : OSC_50
Failed Paths   : 0

Type           : Clock Hold: 'OSC_50'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : LCD_TEST:u1|LUT_INDEX[5]
To             : LCD_TEST:u1|LUT_DATA[3]
From Clock     : OSC_50
To Clock       : OSC_50
Failed Paths   : 54

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 54

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