📄 de2_tv.map.rpt
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; Average fan-out ; 2.12 ;
+---------------------------------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+----------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+----------------------------------------+
; |DE2_LCD ; 105 (0) ; 51 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 101 ; 0 ; |DE2_LCD ;
; |LCD_TEST:u1| ; 105 (86) ; 51 (38) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_LCD|LCD_TEST:u1 ;
; |LCD_Controller:u0| ; 19 (19) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_LCD|LCD_TEST:u1|LCD_Controller:u0 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+----------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------+
; State Machine - |DE2_LCD|LCD_TEST:u1|mLCD_ST ;
+----------------+----------------+----------------+----------------+----------------+
; Name ; mLCD_ST.000011 ; mLCD_ST.000001 ; mLCD_ST.000010 ; mLCD_ST.000000 ;
+----------------+----------------+----------------+----------------+----------------+
; mLCD_ST.000000 ; 0 ; 0 ; 0 ; 0 ;
; mLCD_ST.000010 ; 0 ; 0 ; 1 ; 1 ;
; mLCD_ST.000001 ; 0 ; 1 ; 0 ; 1 ;
; mLCD_ST.000011 ; 1 ; 0 ; 0 ; 1 ;
+----------------+----------------+----------------+----------------+----------------+
+-----------------------------------------------------------+
; State Machine - |DE2_LCD|LCD_TEST:u1|LCD_Controller:u0|ST ;
+-------+-------+-------+-------+---------------------------+
; Name ; ST.11 ; ST.01 ; ST.10 ; ST.00 ;
+-------+-------+-------+-------+---------------------------+
; ST.00 ; 0 ; 0 ; 0 ; 0 ;
; ST.10 ; 0 ; 0 ; 1 ; 1 ;
; ST.01 ; 0 ; 1 ; 0 ; 1 ;
; ST.11 ; 1 ; 0 ; 0 ; 1 ;
+-------+-------+-------+-------+---------------------------+
+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; LCD_TEST:u1|LUT_DATA[8] ; LCD_TEST:u1|WideOr0 ; yes ;
; LCD_TEST:u1|LUT_DATA[0] ; LCD_TEST:u1|WideOr0 ; yes ;
; LCD_TEST:u1|LUT_DATA[1] ; LCD_TEST:u1|WideOr0 ; yes ;
; LCD_TEST:u1|LUT_DATA[2] ; LCD_TEST:u1|WideOr0 ; yes ;
; LCD_TEST:u1|LUT_DATA[3] ; LCD_TEST:u1|WideOr0 ; yes ;
; LCD_TEST:u1|LUT_DATA[4] ; LCD_TEST:u1|WideOr0 ; yes ;
; LCD_TEST:u1|LUT_DATA[5] ; LCD_TEST:u1|WideOr0 ; yes ;
; LCD_TEST:u1|LUT_DATA[6] ; LCD_TEST:u1|WideOr0 ; yes ;
; LCD_TEST:u1|LUT_DATA[7] ; LCD_TEST:u1|WideOr0 ; yes ;
; Number of user-specified and inferred latches = 9 ; ; ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 51 ;
; Number of registers using Synchronous Clear ; 18 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 51 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 45 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |DE2_LCD|LCD_TEST:u1|LCD_Controller:u0|oDone ;
; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |DE2_LCD|LCD_TEST:u1|mLCD_ST~11 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: LCD_TEST:u1 ;
+----------------+-------+---------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------+
; LCD_INTIAL ; 0 ; Integer ;
; LCD_LINE1 ; 5 ; Integer ;
; LCD_CH_LINE ; 21 ; Integer ;
; LCD_LINE2 ; 22 ; Integer ;
; LUT_SIZE ; 38 ; Integer ;
+----------------+-------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: LCD_TEST:u1|LCD_Controller:u0 ;
+----------------+-------+---------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------------------------+
; CLK_Divide ; 16 ; Integer ;
+----------------+-------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Jul 01 20:08:27 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_TV -c DE2_TV
Warning: Can't analyze file -- file F:/DE2_TV/AUDIO_DAC.v is missing
Warning (10238): Verilog Module Declaration warning at DE2_TV.v(29): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "DE2_LCD"
Info: Found 1 design units, including 1 entities, in source file DE2_TV.v
Info: Found entity 1: DE2_LCD
Warning: Can't analyze file -- file F:/DE2_TV/dul_port_c1024.v is missing
Warning: Can't analyze file -- file F:/DE2_TV/I2C_AV_Config.v is missing
Warning: Can't analyze file -- file F:/DE2_TV/I2C_Controller.v is missing
Warning: Can't analyze file -- file F:/DE2_TV/itu_r656_decoder.v is missing
Info: Found 1 design units, including 1 entities, in source file LCD_Controller.v
Info: Found entity 1: LCD_Controller
Info: Found 1 design units, including 1 entities, in source file LCD_TEST.v
Info: Found entity 1: LCD_TEST
Warning: Can't analyze file -- file F:/DE2_TV/MAC_3.v is missing
Warning: Can't analyze file -- file F:/DE2_TV/ram2.v is missing
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v
Info: Found entity 1: SEG7_LUT
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT_8.v
Info: Found entity 1: SEG7_LUT_8
Warning: Can't analyze file -- file F:/DE2_TV/TV_to_VGA.v is missing
Warning: Can't analyze file -- file F:/DE2_TV/VGA_Audio_PLL.v is missing
Warning: Can't analyze file -- file F:/DE2_TV/YCbCr2RGB.v is missing
Info: Elaborating entity "DE2_LCD" for the top level hierarchy
Info: Elaborating entity "SEG7_LUT_8" for hierarchy "SEG7_LUT_8:u0"
Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT_8:u0|SEG7_LUT:u0"
Info: Elaborating entity "LCD_TEST" for hierarchy "LCD_TEST:u1"
Warning (10230): Verilog HDL assignment warning at LCD_TEST.v(57): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at LCD_TEST.v(65): truncated value with size 32 to match size of target (6)
Warning (10270): Verilog HDL statement warning at LCD_TEST.v(75): incomplete Case Statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at LCD_TEST.v(119): inferring latch(es) for variable "LUT_DATA", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for "LUT_DATA[8]"
Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for "LUT_DATA[7]"
Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for "LUT_DATA[6]"
Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for "LUT_DATA[5]"
Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for "LUT_DATA[4]"
Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for "LUT_DATA[3]"
Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for "LUT_DATA[2]"
Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for "LUT_DATA[1]"
Info (10041): Verilog HDL or VHDL info at LCD_TEST.v(75): inferred latch for "LUT_DATA[0]"
Info: Elaborating entity "LCD_Controller" for hierarchy "LCD_TEST:u1|LCD_Controller:u0"
Warning (10230): Verilog HDL assignment warning at LCD_Controller.v(66): truncated value with size 32 to match size of target (5)
Info: State machine "|DE2_LCD|LCD_TEST:u1|mLCD_ST" contains 4 states
Info: State machine "|DE2_LCD|LCD_TEST:u1|LCD_Controller:u0|ST" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|DE2_LCD|LCD_TEST:u1|mLCD_ST"
Info: Encoding result for state machine "|DE2_LCD|LCD_TEST:u1|mLCD_ST"
Info: Completed encoding using 4 state bits
Info: Encoded state bit "LCD_TEST:u1|mLCD_ST.000011"
Info: Encoded state bit "LCD_TEST:u1|mLCD_ST.000001"
Info: Encoded state bit "LCD_TEST:u1|mLCD_ST.000010"
Info: Encoded state bit "LCD_TEST:u1|mLCD_ST.000000"
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