de2_tv.tan.talkback.xml

本源码是用verilog编写控制LCD——使用Quartusii

<!--
This XML file (created on Tue Jul 01 20:09:44 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
	<host_id>00581cf7ea5d</host_id>
	<nic_id>00581cf7ea5d</nic_id>
	<cdrive_id>1c93edea</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 178</build>
	<binary_type>32</binary_type>
	<module>quartus_tan</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Tue Jul 01 20:09:45 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">1596</cpu_freq>
	</cpu>
	<ram units="MB">1016</ram>
</machine>
<project>F:/DE2_TV/DE2_TV</project>
<revision>DE2_TV</revision>
<compilation_summary>
	<flow_status>Successful - Tue Jul 01 20:09:44 2008</flow_status>
	<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Full Version</quartus_ii_version>
	<revision_name>DE2_TV</revision_name>
	<top_level_entity_name>DE2_LCD</top_level_entity_name>
	<family>Cyclone II</family>
	<device>EP2C35F672C8</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>No</met_timing_requirements>
	<total_logic_elements>105 / 33,216 ( &lt; 1 % )</total_logic_elements>
	<total_registers>51</total_registers>
	<total_pins>101 / 475 ( 21 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>0 / 483,840 ( 0 % )</total_memory_bits>
	<embedded_multiplier_9_bit_elements>0 / 70 ( 0 % )</embedded_multiplier_9_bit_elements>
	<total_plls>0 / 4 ( 0 % )</total_plls>
</compilation_summary>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off DE2_TV -c DE2_TV --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Circuit may not operate. Detected 54 non-operational path(s) clocked by clock &quot;OSC_50&quot; with clock skew larger than data delay. See Compilation Report for details.</warning>
	<warning>Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis is analyzing one or more combinational loops as latches</warning>
	<warning>Warning: Node &quot;LCD_TEST:u1|LUT_DATA[7]&quot; is a latch</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 13 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Tue Jul 01 20:09:44 2008</info>
	<info>Info: tco from clock &quot;OSC_50&quot; to destination pin &quot;LCD_DATA[6]&quot; through register &quot;LCD_TEST:u1|mLCD_DATA[6]&quot; is 8.004 ns</info>
	<info>Info: + Longest register to pin delay is 4.517 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>OSC_50</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>8.004 ns</actual>
	</nonclk>
	<clk>
		<name>OSC_50</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>165.54 MHz ( period = 6.041 ns )</actual>
	</clk>
</performance>
</talkback>