dds.map.eqn

实现DDS频率可调得VHDL程序

-- Copyright (C) 1991-2005 Altera Corporation
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--E1_q_a[0] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[0]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = CLK;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out[0];


--E1_q_a[1] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[1]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = CLK;
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[1] = E1_q_a[1]_PORT_A_data_out[0];


--E1_q_a[2] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[2]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[2]_PORT_A_address_reg = DFFE(E1_q_a[2]_PORT_A_address, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_clock_0 = CLK;
E1_q_a[2]_PORT_A_data_out = MEMORY(, , E1_q_a[2]_PORT_A_address_reg, , , , , , E1_q_a[2]_clock_0, , , , , );
E1_q_a[2] = E1_q_a[2]_PORT_A_data_out[0];


--E1_q_a[3] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[3]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[3]_PORT_A_address_reg = DFFE(E1_q_a[3]_PORT_A_address, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_clock_0 = CLK;
E1_q_a[3]_PORT_A_data_out = MEMORY(, , E1_q_a[3]_PORT_A_address_reg, , , , , , E1_q_a[3]_clock_0, , , , , );
E1_q_a[3] = E1_q_a[3]_PORT_A_data_out[0];


--E1_q_a[4] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[4]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[4]_PORT_A_address_reg = DFFE(E1_q_a[4]_PORT_A_address, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_clock_0 = CLK;
E1_q_a[4]_PORT_A_data_out = MEMORY(, , E1_q_a[4]_PORT_A_address_reg, , , , , , E1_q_a[4]_clock_0, , , , , );
E1_q_a[4] = E1_q_a[4]_PORT_A_data_out[0];


--E1_q_a[5] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[5]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[5]_PORT_A_address_reg = DFFE(E1_q_a[5]_PORT_A_address, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_clock_0 = CLK;
E1_q_a[5]_PORT_A_data_out = MEMORY(, , E1_q_a[5]_PORT_A_address_reg, , , , , , E1_q_a[5]_clock_0, , , , , );
E1_q_a[5] = E1_q_a[5]_PORT_A_data_out[0];


--E1_q_a[6] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[6]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[6]_PORT_A_address_reg = DFFE(E1_q_a[6]_PORT_A_address, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_clock_0 = CLK;
E1_q_a[6]_PORT_A_data_out = MEMORY(, , E1_q_a[6]_PORT_A_address_reg, , , , , , E1_q_a[6]_clock_0, , , , , );
E1_q_a[6] = E1_q_a[6]_PORT_A_data_out[0];


--E1_q_a[7] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[7]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = CLK;
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7] = E1_q_a[7]_PORT_A_data_out[0];


--B1_TEMP[8] is SUM:U0|TEMP[8]
--operation mode is arithmetic

B1_TEMP[8]_lut_out = B1_TEMP[8] $ M[0];
B1_TEMP[8] = DFFEAS(B1_TEMP[8]_lut_out, CLK, !RESET, , EN, , , , );

--B1L3 is SUM:U0|TEMP[8]~73
--operation mode is arithmetic

B1L3 = CARRY(B1_TEMP[8] & M[0]);


--B1_TEMP[9] is SUM:U0|TEMP[9]
--operation mode is arithmetic

B1_TEMP[9]_carry_eqn = B1L3;
B1_TEMP[9]_lut_out = B1_TEMP[9] $ M[1] $ B1_TEMP[9]_carry_eqn;
B1_TEMP[9] = DFFEAS(B1_TEMP[9]_lut_out, CLK, !RESET, , EN, , , , );

--B1L5 is SUM:U0|TEMP[9]~77
--operation mode is arithmetic

B1L5 = CARRY(B1_TEMP[9] & !M[1] & !B1L3 # !B1_TEMP[9] & (!B1L3 # !M[1]));


--B1_TEMP[10] is SUM:U0|TEMP[10]
--operation mode is arithmetic

B1_TEMP[10]_carry_eqn = B1L5;
B1_TEMP[10]_lut_out = B1_TEMP[10] $ M[2] $ !B1_TEMP[10]_carry_eqn;
B1_TEMP[10] = DFFEAS(B1_TEMP[10]_lut_out, CLK, !RESET, , EN, , , , );

--B1L7 is SUM:U0|TEMP[10]~81
--operation mode is arithmetic

B1L7 = CARRY(B1_TEMP[10] & (M[2] # !B1L5) # !B1_TEMP[10] & M[2] & !B1L5);


--B1_TEMP[11] is SUM:U0|TEMP[11]
--operation mode is arithmetic

B1_TEMP[11]_carry_eqn = B1L7;
B1_TEMP[11]_lut_out = B1_TEMP[11] $ M[3] $ B1_TEMP[11]_carry_eqn;
B1_TEMP[11] = DFFEAS(B1_TEMP[11]_lut_out, CLK, !RESET, , EN, , , , );

--B1L9 is SUM:U0|TEMP[11]~85
--operation mode is arithmetic

B1L9 = CARRY(B1_TEMP[11] & !M[3] & !B1L7 # !B1_TEMP[11] & (!B1L7 # !M[3]));


--B1_TEMP[12] is SUM:U0|TEMP[12]
--operation mode is arithmetic

B1_TEMP[12]_carry_eqn = B1L9;
B1_TEMP[12]_lut_out = B1_TEMP[12] $ M[4] $ !B1_TEMP[12]_carry_eqn;
B1_TEMP[12] = DFFEAS(B1_TEMP[12]_lut_out, CLK, !RESET, , EN, , , , );

--B1L11 is SUM:U0|TEMP[12]~89
--operation mode is arithmetic

B1L11 = CARRY(B1_TEMP[12] & (M[4] # !B1L9) # !B1_TEMP[12] & M[4] & !B1L9);


--B1_TEMP[13] is SUM:U0|TEMP[13]
--operation mode is arithmetic

B1_TEMP[13]_carry_eqn = B1L11;
B1_TEMP[13]_lut_out = B1_TEMP[13] $ M[5] $ B1_TEMP[13]_carry_eqn;
B1_TEMP[13] = DFFEAS(B1_TEMP[13]_lut_out, CLK, !RESET, , EN, , , , );

--B1L31 is SUM:U0|TEMP[13]~93
--operation mode is arithmetic

B1L31 = CARRY(B1_TEMP[13] & !M[5] & !B1L11 # !B1_TEMP[13] & (!B1L11 # !M[5]));


--B1_TEMP[14] is SUM:U0|TEMP[14]
--operation mode is arithmetic

B1_TEMP[14]_carry_eqn = B1L31;
B1_TEMP[14]_lut_out = B1_TEMP[14] $ M[6] $ !B1_TEMP[14]_carry_eqn;
B1_TEMP[14] = DFFEAS(B1_TEMP[14]_lut_out, CLK, !RESET, , EN, , , , );

--B1L51 is SUM:U0|TEMP[14]~97
--operation mode is arithmetic

B1L51 = CARRY(B1_TEMP[14] & (M[6] # !B1L31) # !B1_TEMP[14] & M[6] & !B1L31);


--B1_TEMP[15] is SUM:U0|TEMP[15]
--operation mode is normal

B1_TEMP[15]_carry_eqn = B1L51;
B1_TEMP[15]_lut_out = B1_TEMP[15] $ M[7] $ B1_TEMP[15]_carry_eqn;
B1_TEMP[15] = DFFEAS(B1_TEMP[15]_lut_out, CLK, !RESET, , EN, , , , );


--~GND is ~GND
--operation mode is normal

~GND = GND;


--CLK is CLK
--operation mode is input

CLK = INPUT();


--M[0] is M[0]
--operation mode is input

M[0] = INPUT();


--RESET is RESET
--operation mode is input

RESET = INPUT();


--EN is EN
--operation mode is input

EN = INPUT();


--M[1] is M[1]
--operation mode is input

M[1] = INPUT();


--M[2] is M[2]
--operation mode is input

M[2] = INPUT();


--M[3] is M[3]
--operation mode is input

M[3] = INPUT();


--M[4] is M[4]
--operation mode is input

M[4] = INPUT();


--M[5] is M[5]
--operation mode is input

M[5] = INPUT();


--M[6] is M[6]
--operation mode is input

M[6] = INPUT();


--M[7] is M[7]
--operation mode is input

M[7] = INPUT();


--Q[0] is Q[0]
--operation mode is output

Q[0] = OUTPUT(E1_q_a[0]);


--Q[1] is Q[1]
--operation mode is output

Q[1] = OUTPUT(E1_q_a[1]);


--Q[2] is Q[2]
--operation mode is output

Q[2] = OUTPUT(E1_q_a[2]);


--Q[3] is Q[3]
--operation mode is output

Q[3] = OUTPUT(E1_q_a[3]);


--Q[4] is Q[4]
--operation mode is output

Q[4] = OUTPUT(E1_q_a[4]);


--Q[5] is Q[5]
--operation mode is output

Q[5] = OUTPUT(E1_q_a[5]);


--Q[6] is Q[6]
--operation mode is output

Q[6] = OUTPUT(E1_q_a[6]);


--Q[7] is Q[7]
--operation mode is output

Q[7] = OUTPUT(E1_q_a[7]);