📄 dds.map.rpt
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; Total memory bits ; 8192 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 16 ;
; Total fan-out ; 135 ;
; Average fan-out ; 3.75 ;
+-----------------------------------+---------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------+
; |DDS ; 9 (1) ; 8 ; 8192 ; 19 ; 0 ; 1 (1) ; 0 (0) ; 8 (0) ; 8 (0) ; |DDS ;
; |SUM:U0| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; |DDS|SUM:U0 ;
; |rom:U2| ; 0 (0) ; 0 ; 8192 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS|rom:U2 ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 8192 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS|rom:U2|altsyncram:altsyncram_component ;
; |altsyncram_tdq:auto_generated| ; 0 (0) ; 0 ; 8192 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS|rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+---------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+---------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+---------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+---------+
; rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 1024 ; 8 ; -- ; -- ; 8192 ; rom.mif ;
+---------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+---------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 8 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 8 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 8 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom:U2|altsyncram:altsyncram_component ;
+------------------------------------+----------------+-------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------+-------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 8 ; Integer ;
; WIDTHAD_A ; 10 ; Integer ;
; NUMWORDS_A ; 1024 ; Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; rom.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_tdq ; Untyped ;
+------------------------------------+----------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Tue May 27 18:15:29 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS
Info: Found 2 design units, including 1 entities, in source file rom.vhd
Info: Found design unit 1: rom-SYN
Info: Found entity 1: rom
Info: Found 2 design units, including 1 entities, in source file DDS.vhd
Info: Found design unit 1: DDS-ART
Info: Found entity 1: DDS
Info: Found 2 design units, including 1 entities, in source file SUM.vhd
Info: Found design unit 1: SUM-ONE
Info: Found entity 1: SUM
Info: Elaborating entity "DDS" for the top level hierarchy
Info: Elaborating entity "SUM" for hierarchy "SUM:U0"
Warning: VHDL Process Statement warning at SUM.vhd(19): signal "K" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at SUM.vhd(31): signal "TEMP" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "rom" for hierarchy "rom:U2"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus50/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "rom:U2|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tdq.tdf
Info: Found entity 1: altsyncram_tdq
Info: Elaborating entity "altsyncram_tdq" for hierarchy "rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated"
Warning: Reduced register "SUM:U0|TEMP[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "SUM:U0|TEMP[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "SUM:U0|TEMP[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "SUM:U0|TEMP[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "SUM:U0|TEMP[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "SUM:U0|TEMP[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "SUM:U0|TEMP[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "SUM:U0|TEMP[0]" with stuck data_in port to stuck value GND
Info: Implemented 36 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 8 output pins
Info: Implemented 9 logic cells
Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
Info: Processing ended: Tue May 27 18:15:31 2008
Info: Elapsed time: 00:00:02
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