dds.fit.summary

来自「实现DDS频率可调得VHDL程序」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Tue May 27 18:15:35 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : DDS
Top-level Entity Name : DDS
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 9 / 2,910 ( < 1 % )
Total pins : 19 / 104 ( 18 % )
Total virtual pins : 0
Total memory bits : 8,192 / 59,904 ( 13 % )
Total PLLs : 0 / 1 ( 0 % )