dds.hier_info

实现DDS频率可调得VHDL程序

|DDS
M[0] => SUM:U0.K[0]
M[1] => SUM:U0.K[1]
M[2] => SUM:U0.K[2]
M[3] => SUM:U0.K[3]
M[4] => SUM:U0.K[4]
M[5] => SUM:U0.K[5]
M[6] => SUM:U0.K[6]
M[7] => SUM:U0.K[7]
EN => SUM:U0.EN
RESET => SUM:U0.RESET
CLK => ROM:U2.inclock
CLK => SUM:U0.CLK
Q[0] <= ROM:U2.q[0]
Q[1] <= ROM:U2.q[1]
Q[2] <= ROM:U2.q[2]
Q[3] <= ROM:U2.q[3]
Q[4] <= ROM:U2.q[4]
Q[5] <= ROM:U2.q[5]
Q[6] <= ROM:U2.q[6]
Q[7] <= ROM:U2.q[7]


|DDS|SUM:U0
K[0] => add~0.IN32
K[1] => add~0.IN31
K[2] => add~0.IN30
K[3] => add~0.IN29
K[4] => add~0.IN28
K[5] => add~0.IN27
K[6] => add~0.IN26
K[7] => add~0.IN25
CLK => TEMP[14].CLK
CLK => TEMP[13].CLK
CLK => TEMP[12].CLK
CLK => TEMP[11].CLK
CLK => TEMP[10].CLK
CLK => TEMP[9].CLK
CLK => TEMP[8].CLK
CLK => TEMP[7].CLK
CLK => TEMP[6].CLK
CLK => TEMP[5].CLK
CLK => TEMP[4].CLK
CLK => TEMP[3].CLK
CLK => TEMP[2].CLK
CLK => TEMP[1].CLK
CLK => TEMP[0].CLK
CLK => TEMP[15].CLK
EN => TEMP[14].ENA
EN => TEMP[13].ENA
EN => TEMP[12].ENA
EN => TEMP[11].ENA
EN => TEMP[10].ENA
EN => TEMP[9].ENA
EN => TEMP[8].ENA
EN => TEMP[7].ENA
EN => TEMP[6].ENA
EN => TEMP[5].ENA
EN => TEMP[4].ENA
EN => TEMP[3].ENA
EN => TEMP[2].ENA
EN => TEMP[1].ENA
EN => TEMP[0].ENA
EN => TEMP[15].ENA
RESET => TEMP[14].ACLR
RESET => TEMP[13].ACLR
RESET => TEMP[12].ACLR
RESET => TEMP[11].ACLR
RESET => TEMP[10].ACLR
RESET => TEMP[9].ACLR
RESET => TEMP[8].ACLR
RESET => TEMP[7].ACLR
RESET => TEMP[6].ACLR
RESET => TEMP[5].ACLR
RESET => TEMP[4].ACLR
RESET => TEMP[3].ACLR
RESET => TEMP[2].ACLR
RESET => TEMP[1].ACLR
RESET => TEMP[0].ACLR
RESET => TEMP[15].ACLR
OUT1[0] <= TEMP[0].DB_MAX_OUTPUT_PORT_TYPE
OUT1[1] <= TEMP[1].DB_MAX_OUTPUT_PORT_TYPE
OUT1[2] <= TEMP[2].DB_MAX_OUTPUT_PORT_TYPE
OUT1[3] <= TEMP[3].DB_MAX_OUTPUT_PORT_TYPE
OUT1[4] <= TEMP[4].DB_MAX_OUTPUT_PORT_TYPE
OUT1[5] <= TEMP[5].DB_MAX_OUTPUT_PORT_TYPE
OUT1[6] <= TEMP[6].DB_MAX_OUTPUT_PORT_TYPE
OUT1[7] <= TEMP[7].DB_MAX_OUTPUT_PORT_TYPE
OUT1[8] <= TEMP[8].DB_MAX_OUTPUT_PORT_TYPE
OUT1[9] <= TEMP[9].DB_MAX_OUTPUT_PORT_TYPE
OUT1[10] <= TEMP[10].DB_MAX_OUTPUT_PORT_TYPE
OUT1[11] <= TEMP[11].DB_MAX_OUTPUT_PORT_TYPE
OUT1[12] <= TEMP[12].DB_MAX_OUTPUT_PORT_TYPE
OUT1[13] <= TEMP[13].DB_MAX_OUTPUT_PORT_TYPE
OUT1[14] <= TEMP[14].DB_MAX_OUTPUT_PORT_TYPE
OUT1[15] <= TEMP[15].DB_MAX_OUTPUT_PORT_TYPE


|DDS|rom:U2
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|DDS|rom:U2|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_tdq:auto_generated.address_a[0]
address_a[1] => altsyncram_tdq:auto_generated.address_a[1]
address_a[2] => altsyncram_tdq:auto_generated.address_a[2]
address_a[3] => altsyncram_tdq:auto_generated.address_a[3]
address_a[4] => altsyncram_tdq:auto_generated.address_a[4]
address_a[5] => altsyncram_tdq:auto_generated.address_a[5]
address_a[6] => altsyncram_tdq:auto_generated.address_a[6]
address_a[7] => altsyncram_tdq:auto_generated.address_a[7]
address_a[8] => altsyncram_tdq:auto_generated.address_a[8]
address_a[9] => altsyncram_tdq:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_tdq:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_tdq:auto_generated.q_a[0]
q_a[1] <= altsyncram_tdq:auto_generated.q_a[1]
q_a[2] <= altsyncram_tdq:auto_generated.q_a[2]
q_a[3] <= altsyncram_tdq:auto_generated.q_a[3]
q_a[4] <= altsyncram_tdq:auto_generated.q_a[4]
q_a[5] <= altsyncram_tdq:auto_generated.q_a[5]
q_a[6] <= altsyncram_tdq:auto_generated.q_a[6]
q_a[7] <= altsyncram_tdq:auto_generated.q_a[7]
q_b[0] <= <GND>


|DDS|rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT