dds.fit.qmsg

实现DDS频率可调得VHDL程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 27 18:15:32 2008 " "Info: Processing started: Tue May 27 18:15:32 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DDS -c DDS " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DDS -c DDS" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DDS EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"DDS\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN 93 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN 93" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 9 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RESET Global clock " "Info: Automatically promoted signal \"RESET\" to use Global clock" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "RESET " "Info: Pin \"RESET\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RESET" } } } } { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { RESET } "NODE_NAME" } "" } } { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.fld" "" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.fld" "" "" { RESET } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.442 ns register register " "Info: Estimated most critical path is register to register delay of 2.442 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SUM:U0\|TEMP\[8\] 1 REG LAB_X15_Y1 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y1; Fanout = 11; REG Node = 'SUM:U0\|TEMP\[8\]'" {  } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { SUM:U0|TEMP[8] } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.471 ns) + CELL(0.575 ns) 1.046 ns SUM:U0\|TEMP\[8\]~73COUT1_105 2 COMB LAB_X15_Y1 2 " "Info: 2: + IC(0.471 ns) + CELL(0.575 ns) = 1.046 ns; Loc. = LAB_X15_Y1; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[8\]~73COUT1_105'" {  } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "1.046 ns" { SUM:U0|TEMP[8] SUM:U0|TEMP[8]~73COUT1_105 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.126 ns SUM:U0\|TEMP\[9\]~77COUT1_106 3 COMB LAB_X15_Y1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.126 ns; Loc. = LAB_X15_Y1; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[9\]~77COUT1_106'" {  } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.080 ns" { SUM:U0|TEMP[8]~73COUT1_105 SUM:U0|TEMP[9]~77COUT1_106 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.206 ns SUM:U0\|TEMP\[10\]~81COUT1_107 4 COMB LAB_X15_Y1 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.206 ns; Loc. = LAB_X15_Y1; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[10\]~81COUT1_107'" {  } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.080 ns" { SUM:U0|TEMP[9]~77COUT1_106 SUM:U0|TEMP[10]~81COUT1_107 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.286 ns SUM:U0\|TEMP\[11\]~85COUT1 5 COMB LAB_X15_Y1 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.286 ns; Loc. = LAB_X15_Y1; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[11\]~85COUT1'" {  } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.080 ns" { SUM:U0|TEMP[10]~81COUT1_107 SUM:U0|TEMP[11]~85COUT1 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.544 ns SUM:U0\|TEMP\[12\]~89 6 COMB LAB_X15_Y1 3 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.544 ns; Loc. = LAB_X15_Y1; Fanout = 3; COMB Node = 'SUM:U0\|TEMP\[12\]~89'" {  } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.258 ns" { SUM:U0|TEMP[11]~85COUT1 SUM:U0|TEMP[12]~89 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.442 ns SUM:U0\|TEMP\[13\] 7 REG LAB_X15_Y1 11 " "Info: 7: + IC(0.000 ns) + CELL(0.898 ns) = 2.442 ns; Loc. = LAB_X15_Y1; Fanout = 11; REG Node = 'SUM:U0\|TEMP\[13\]'" {  } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.898 ns" { SUM:U0|TEMP[12]~89 SUM:U0|TEMP[13] } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.971 ns 80.71 % " "Info: Total cell delay = 1.971 ns ( 80.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.471 ns 19.29 % " "Info: Total interconnect delay = 0.471 ns ( 19.29 % )" {  } {  } 0}  } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.442 ns" { SUM:U0|TEMP[8] SUM:U0|TEMP[8]~73COUT1_105 SUM:U0|TEMP[9]~77COUT1_106 SUM:U0|TEMP[10]~81COUT1_107 SUM:U0|TEMP[11]~85COUT1 SUM:U0|TEMP[12]~89 SUM:U0|TEMP[13] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 27 18:15:35 2008 " "Info: Processing ended: Tue May 27 18:15:35 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}