dds.map.qmsg

实现DDS频率可调得VHDL程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 27 18:15:29 2008 " "Info: Processing started: Tue May 27 18:15:29 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom-SYN " "Info: Found design unit 1: rom-SYN" {  } { { "rom.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/rom.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rom " "Info: Found entity 1: rom" {  } { { "rom.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/rom.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DDS.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDS-ART " "Info: Found design unit 1: DDS-ART" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DDS " "Info: Found entity 1: DDS" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SUM.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SUM.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SUM-ONE " "Info: Found design unit 1: SUM-ONE" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 SUM " "Info: Found entity 1: SUM" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDS " "Info: Elaborating entity \"DDS\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SUM SUM:U0 " "Info: Elaborating entity \"SUM\" for hierarchy \"SUM:U0\"" {  } { { "DDS.vhd" "U0" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 42 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "K SUM.vhd(19) " "Warning: VHDL Process Statement warning at SUM.vhd(19): signal \"K\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TEMP SUM.vhd(31) " "Warning: VHDL Process Statement warning at SUM.vhd(31): signal \"TEMP\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 31 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:U2 " "Info: Elaborating entity \"rom\" for hierarchy \"rom:U2\"" {  } { { "DDS.vhd" "U2" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 44 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom:U2\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rom:U2\|altsyncram:altsyncram_component\"" {  } { { "rom.vhd" "altsyncram_component" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/rom.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_tdq.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tdq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_tdq " "Info: Found entity 1: altsyncram_tdq" {  } { { "db/altsyncram_tdq.tdf" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/altsyncram_tdq.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_tdq rom:U2\|altsyncram:altsyncram_component\|altsyncram_tdq:auto_generated " "Info: Elaborating entity \"altsyncram_tdq\" for hierarchy \"rom:U2\|altsyncram:altsyncram_component\|altsyncram_tdq:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SUM:U0\|TEMP\[7\] data_in GND " "Warning: Reduced register \"SUM:U0\|TEMP\[7\]\" with stuck data_in port to stuck value GND" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SUM:U0\|TEMP\[6\] data_in GND " "Warning: Reduced register \"SUM:U0\|TEMP\[6\]\" with stuck data_in port to stuck value GND" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SUM:U0\|TEMP\[5\] data_in GND " "Warning: Reduced register \"SUM:U0\|TEMP\[5\]\" with stuck data_in port to stuck value GND" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SUM:U0\|TEMP\[4\] data_in GND " "Warning: Reduced register \"SUM:U0\|TEMP\[4\]\" with stuck data_in port to stuck value GND" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SUM:U0\|TEMP\[3\] data_in GND " "Warning: Reduced register \"SUM:U0\|TEMP\[3\]\" with stuck data_in port to stuck value GND" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SUM:U0\|TEMP\[2\] data_in GND " "Warning: Reduced register \"SUM:U0\|TEMP\[2\]\" with stuck data_in port to stuck value GND" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SUM:U0\|TEMP\[1\] data_in GND " "Warning: Reduced register \"SUM:U0\|TEMP\[1\]\" with stuck data_in port to stuck value GND" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SUM:U0\|TEMP\[0\] data_in GND " "Warning: Reduced register \"SUM:U0\|TEMP\[0\]\" with stuck data_in port to stuck value GND" {  } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "36 " "Info: Implemented 36 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "9 " "Info: Implemented 9 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 27 18:15:31 2008 " "Info: Processing ended: Tue May 27 18:15:31 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}