📄 dds.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register SUM:U0\|TEMP\[9\] SUM:U0\|TEMP\[15\] 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"SUM:U0\|TEMP\[9\]\" and destination register \"SUM:U0\|TEMP\[15\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.271 ns + Longest register register " "Info: + Longest register to register delay is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SUM:U0\|TEMP\[9\] 1 REG LC_X15_Y1_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y1_N1; Fanout = 5; REG Node = 'SUM:U0\|TEMP\[9\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { SUM:U0|TEMP[9] } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.564 ns) 1.098 ns SUM:U0\|TEMP\[9\]~77 2 COMB LC_X15_Y1_N1 2 " "Info: 2: + IC(0.534 ns) + CELL(0.564 ns) = 1.098 ns; Loc. = LC_X15_Y1_N1; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[9\]~77'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "1.098 ns" { SUM:U0|TEMP[9] SUM:U0|TEMP[9]~77 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.176 ns SUM:U0\|TEMP\[10\]~81 3 COMB LC_X15_Y1_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.176 ns; Loc. = LC_X15_Y1_N2; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[10\]~81'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.078 ns" { SUM:U0|TEMP[9]~77 SUM:U0|TEMP[10]~81 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.254 ns SUM:U0\|TEMP\[11\]~85 4 COMB LC_X15_Y1_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.254 ns; Loc. = LC_X15_Y1_N3; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[11\]~85'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.078 ns" { SUM:U0|TEMP[10]~81 SUM:U0|TEMP[11]~85 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.432 ns SUM:U0\|TEMP\[12\]~89 5 COMB LC_X15_Y1_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.432 ns; Loc. = LC_X15_Y1_N4; Fanout = 3; COMB Node = 'SUM:U0\|TEMP\[12\]~89'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.178 ns" { SUM:U0|TEMP[11]~85 SUM:U0|TEMP[12]~89 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.271 ns SUM:U0\|TEMP\[15\] 6 REG LC_X15_Y1_N7 3 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.271 ns; Loc. = LC_X15_Y1_N7; Fanout = 3; REG Node = 'SUM:U0\|TEMP\[15\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.839 ns" { SUM:U0|TEMP[12]~89 SUM:U0|TEMP[15] } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns 76.49 % " "Info: Total cell delay = 1.737 ns ( 76.49 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.534 ns 23.51 % " "Info: Total interconnect delay = 0.534 ns ( 23.51 % )" { } { } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.271 ns" { SUM:U0|TEMP[9] SUM:U0|TEMP[9]~77 SUM:U0|TEMP[10]~81 SUM:U0|TEMP[11]~85 SUM:U0|TEMP[12]~89 SUM:U0|TEMP[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.271 ns" { SUM:U0|TEMP[9] SUM:U0|TEMP[9]~77 SUM:U0|TEMP[10]~81 SUM:U0|TEMP[11]~85 SUM:U0|TEMP[12]~89 SUM:U0|TEMP[15] } { 0.000ns 0.534ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.743 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 28; CLK Node = 'CLK'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns SUM:U0\|TEMP\[15\] 2 REG LC_X15_Y1_N7 3 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y1_N7; Fanout = 3; REG Node = 'SUM:U0\|TEMP\[15\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "1.274 ns" { CLK SUM:U0|TEMP[15] } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.48 % " "Info: Total cell delay = 2.180 ns ( 79.48 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns 20.52 % " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" { } { } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.743 ns" { CLK SUM:U0|TEMP[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.743 ns" { CLK CLK~out0 SUM:U0|TEMP[15] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.743 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 28; CLK Node = 'CLK'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns SUM:U0\|TEMP\[9\] 2 REG LC_X15_Y1_N1 5 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y1_N1; Fanout = 5; REG Node = 'SUM:U0\|TEMP\[9\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "1.274 ns" { CLK SUM:U0|TEMP[9] } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.48 % " "Info: Total cell delay = 2.180 ns ( 79.48 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns 20.52 % " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" { } { } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.743 ns" { CLK SUM:U0|TEMP[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.743 ns" { CLK CLK~out0 SUM:U0|TEMP[9] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.743 ns" { CLK SUM:U0|TEMP[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.743 ns" { CLK CLK~out0 SUM:U0|TEMP[15] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.743 ns" { CLK SUM:U0|TEMP[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.743 ns" { CLK CLK~out0 SUM:U0|TEMP[9] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.271 ns" { SUM:U0|TEMP[9] SUM:U0|TEMP[9]~77 SUM:U0|TEMP[10]~81 SUM:U0|TEMP[11]~85 SUM:U0|TEMP[12]~89 SUM:U0|TEMP[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.271 ns" { SUM:U0|TEMP[9] SUM:U0|TEMP[9]~77 SUM:U0|TEMP[10]~81 SUM:U0|TEMP[11]~85 SUM:U0|TEMP[12]~89 SUM:U0|TEMP[15] } { 0.000ns 0.534ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.743 ns" { CLK SUM:U0|TEMP[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.743 ns" { CLK CLK~out0 SUM:U0|TEMP[15] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.743 ns" { CLK SUM:U0|TEMP[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.743 ns" { CLK CLK~out0 SUM:U0|TEMP[9] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { SUM:U0|TEMP[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { SUM:U0|TEMP[15] } { } { } } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "SUM:U0\|TEMP\[13\] M\[0\] CLK 7.968 ns register " "Info: tsu for register \"SUM:U0\|TEMP\[13\]\" (data pin = \"M\[0\]\", clock pin = \"CLK\") is 7.968 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.674 ns + Longest pin register " "Info: + Longest pin to register delay is 10.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns M\[0\] 1 PIN PIN_1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 3; PIN Node = 'M\[0\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { M[0] } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.390 ns) + CELL(0.564 ns) 9.423 ns SUM:U0\|TEMP\[8\]~73 2 COMB LC_X15_Y1_N0 2 " "Info: 2: + IC(7.390 ns) + CELL(0.564 ns) = 9.423 ns; Loc. = LC_X15_Y1_N0; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[8\]~73'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "7.954 ns" { M[0] SUM:U0|TEMP[8]~73 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 9.501 ns SUM:U0\|TEMP\[9\]~77 3 COMB LC_X15_Y1_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 9.501 ns; Loc. = LC_X15_Y1_N1; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[9\]~77'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.078 ns" { SUM:U0|TEMP[8]~73 SUM:U0|TEMP[9]~77 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 9.579 ns SUM:U0\|TEMP\[10\]~81 4 COMB LC_X15_Y1_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 9.579 ns; Loc. = LC_X15_Y1_N2; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[10\]~81'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.078 ns" { SUM:U0|TEMP[9]~77 SUM:U0|TEMP[10]~81 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 9.657 ns SUM:U0\|TEMP\[11\]~85 5 COMB LC_X15_Y1_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 9.657 ns; Loc. = LC_X15_Y1_N3; Fanout = 2; COMB Node = 'SUM:U0\|TEMP\[11\]~85'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.078 ns" { SUM:U0|TEMP[10]~81 SUM:U0|TEMP[11]~85 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 9.835 ns SUM:U0\|TEMP\[12\]~89 6 COMB LC_X15_Y1_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 9.835 ns; Loc. = LC_X15_Y1_N4; Fanout = 3; COMB Node = 'SUM:U0\|TEMP\[12\]~89'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.178 ns" { SUM:U0|TEMP[11]~85 SUM:U0|TEMP[12]~89 } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 10.674 ns SUM:U0\|TEMP\[13\] 7 REG LC_X15_Y1_N5 5 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 10.674 ns; Loc. = LC_X15_Y1_N5; Fanout = 5; REG Node = 'SUM:U0\|TEMP\[13\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "0.839 ns" { SUM:U0|TEMP[12]~89 SUM:U0|TEMP[13] } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.284 ns 30.77 % " "Info: Total cell delay = 3.284 ns ( 30.77 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.390 ns 69.23 % " "Info: Total interconnect delay = 7.390 ns ( 69.23 % )" { } { } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "10.674 ns" { M[0] SUM:U0|TEMP[8]~73 SUM:U0|TEMP[9]~77 SUM:U0|TEMP[10]~81 SUM:U0|TEMP[11]~85 SUM:U0|TEMP[12]~89 SUM:U0|TEMP[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.674 ns" { M[0] M[0]~out0 SUM:U0|TEMP[8]~73 SUM:U0|TEMP[9]~77 SUM:U0|TEMP[10]~81 SUM:U0|TEMP[11]~85 SUM:U0|TEMP[12]~89 SUM:U0|TEMP[13] } { 0.000ns 0.000ns 7.390ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.564ns 0.078ns 0.078ns 0.078ns 0.178ns 0.839ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.743 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 28; CLK Node = 'CLK'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns SUM:U0\|TEMP\[13\] 2 REG LC_X15_Y1_N5 5 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y1_N5; Fanout = 5; REG Node = 'SUM:U0\|TEMP\[13\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "1.274 ns" { CLK SUM:U0|TEMP[13] } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.48 % " "Info: Total cell delay = 2.180 ns ( 79.48 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns 20.52 % " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" { } { } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.743 ns" { CLK SUM:U0|TEMP[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.743 ns" { CLK CLK~out0 SUM:U0|TEMP[13] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "10.674 ns" { M[0] SUM:U0|TEMP[8]~73 SUM:U0|TEMP[9]~77 SUM:U0|TEMP[10]~81 SUM:U0|TEMP[11]~85 SUM:U0|TEMP[12]~89 SUM:U0|TEMP[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.674 ns" { M[0] M[0]~out0 SUM:U0|TEMP[8]~73 SUM:U0|TEMP[9]~77 SUM:U0|TEMP[10]~81 SUM:U0|TEMP[11]~85 SUM:U0|TEMP[12]~89 SUM:U0|TEMP[13] } { 0.000ns 0.000ns 7.390ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.564ns 0.078ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.743 ns" { CLK SUM:U0|TEMP[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.743 ns" { CLK CLK~out0 SUM:U0|TEMP[13] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[4\] rom:U2\|altsyncram:altsyncram_component\|altsyncram_tdq:auto_generated\|ram_block1a1~porta_address_reg0 12.075 ns memory " "Info: tco from clock \"CLK\" to destination pin \"Q\[4\]\" through memory \"rom:U2\|altsyncram:altsyncram_component\|altsyncram_tdq:auto_generated\|ram_block1a1~porta_address_reg0\" is 12.075 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.754 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to source memory is 2.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 28; CLK Node = 'CLK'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.722 ns) 2.754 ns rom:U2\|altsyncram:altsyncram_component\|altsyncram_tdq:auto_generated\|ram_block1a1~porta_address_reg0 2 MEM M4K_X13_Y2 4 " "Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y2; Fanout = 4; MEM Node = 'rom:U2\|altsyncram:altsyncram_component\|altsyncram_tdq:auto_generated\|ram_block1a1~porta_address_reg0'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "1.285 ns" { CLK rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_tdq.tdf" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/altsyncram_tdq.tdf" 60 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 79.56 % " "Info: Total cell delay = 2.191 ns ( 79.56 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns 20.44 % " "Info: Total interconnect delay = 0.563 ns ( 20.44 % )" { } { } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.754 ns" { CLK rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.754 ns" { CLK CLK~out0 rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" { } { { "db/altsyncram_tdq.tdf" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/altsyncram_tdq.tdf" 60 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.671 ns + Longest memory pin " "Info: + Longest memory to pin delay is 8.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rom:U2\|altsyncram:altsyncram_component\|altsyncram_tdq:auto_generated\|ram_block1a1~porta_address_reg0 1 MEM M4K_X13_Y2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y2; Fanout = 4; MEM Node = 'rom:U2\|altsyncram:altsyncram_component\|altsyncram_tdq:auto_generated\|ram_block1a1~porta_address_reg0'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_tdq.tdf" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/altsyncram_tdq.tdf" 60 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns rom:U2\|altsyncram:altsyncram_component\|altsyncram_tdq:auto_generated\|q_a\[4\] 2 MEM M4K_X13_Y2 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y2; Fanout = 1; MEM Node = 'rom:U2\|altsyncram:altsyncram_component\|altsyncram_tdq:auto_generated\|q_a\[4\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "4.308 ns" { rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[4] } "NODE_NAME" } "" } } { "db/altsyncram_tdq.tdf" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/altsyncram_tdq.tdf" 38 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.255 ns) + CELL(2.108 ns) 8.671 ns Q\[4\] 3 PIN PIN_69 0 " "Info: 3: + IC(2.255 ns) + CELL(2.108 ns) = 8.671 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'Q\[4\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "4.363 ns" { rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[4] Q[4] } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.416 ns 73.99 % " "Info: Total cell delay = 6.416 ns ( 73.99 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.255 ns 26.01 % " "Info: Total interconnect delay = 2.255 ns ( 26.01 % )" { } { } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "8.671 ns" { rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[4] Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.671 ns" { rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[4] Q[4] } { 0.000ns 0.000ns 2.255ns } { 0.000ns 4.308ns 2.108ns } } } } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.754 ns" { CLK rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.754 ns" { CLK CLK~out0 rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } } } { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "8.671 ns" { rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[4] Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.671 ns" { rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0 rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[4] Q[4] } { 0.000ns 0.000ns 2.255ns } { 0.000ns 4.308ns 2.108ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "SUM:U0\|TEMP\[8\] EN CLK -5.673 ns register " "Info: th for register \"SUM:U0\|TEMP\[8\]\" (data pin = \"EN\", clock pin = \"CLK\") is -5.673 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.743 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 28; CLK Node = 'CLK'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns SUM:U0\|TEMP\[8\] 2 REG LC_X15_Y1_N0 5 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y1_N0; Fanout = 5; REG Node = 'SUM:U0\|TEMP\[8\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "1.274 ns" { CLK SUM:U0|TEMP[8] } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.48 % " "Info: Total cell delay = 2.180 ns ( 79.48 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns 20.52 % " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" { } { } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.743 ns" { CLK SUM:U0|TEMP[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.743 ns" { CLK CLK~out0 SUM:U0|TEMP[8] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.431 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.431 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns EN 1 PIN PIN_36 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_36; Fanout = 8; PIN Node = 'EN'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "" { EN } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/DDS.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.095 ns) + CELL(0.867 ns) 8.431 ns SUM:U0\|TEMP\[8\] 2 REG LC_X15_Y1_N0 5 " "Info: 2: + IC(6.095 ns) + CELL(0.867 ns) = 8.431 ns; Loc. = LC_X15_Y1_N0; Fanout = 5; REG Node = 'SUM:U0\|TEMP\[8\]'" { } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "6.962 ns" { EN SUM:U0|TEMP[8] } "NODE_NAME" } "" } } { "SUM.vhd" "" { Text "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/SUM.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 27.71 % " "Info: Total cell delay = 2.336 ns ( 27.71 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.095 ns 72.29 % " "Info: Total interconnect delay = 6.095 ns ( 72.29 % )" { } { } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "8.431 ns" { EN SUM:U0|TEMP[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.431 ns" { EN EN~out0 SUM:U0|TEMP[8] } { 0.000ns 0.000ns 6.095ns } { 0.000ns 1.469ns 0.867ns } } } } 0} } { { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "2.743 ns" { CLK SUM:U0|TEMP[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.743 ns" { CLK CLK~out0 SUM:U0|TEMP[8] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" "" { Report "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/qrxt24/桌面/DDS1024/DDS/" "" "8.431 ns" { EN SUM:U0|TEMP[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.431 ns" { EN EN~out0 SUM:U0|TEMP[8] } { 0.000ns 0.000ns 6.095ns } { 0.000ns 1.469ns 0.867ns } } } } 0}
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