dds.fit.rpt

实现DDS频率可调得VHDL程序

+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage                 ;
+----------------------------+-----------------------+
; C4s                        ; 43 / 8,840 ( < 1 % )  ;
; Direct links               ; 9 / 11,506 ( < 1 % )  ;
; Global clocks              ; 2 / 8 ( 25 % )        ;
; LAB clocks                 ; 3 / 156 ( 1 % )       ;
; LUT chains                 ; 0 / 2,619 ( 0 % )     ;
; Local interconnects        ; 36 / 11,506 ( < 1 % ) ;
; M4K buffers                ; 8 / 468 ( 1 % )       ;
; R4s                        ; 63 / 7,520 ( < 1 % )  ;
+----------------------------+-----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 4.50) ; Number of LABs  (Total = 2) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 1                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 0                           ;
; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 1                           ;
; 9                                          ; 0                           ;
; 10                                         ; 0                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.50) ; Number of LABs  (Total = 2) ;
+------------------------------------+-----------------------------+
; 1 Async. clear                     ; 1                           ;
; 1 Clock                            ; 1                           ;
; 1 Clock enable                     ; 1                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 4.50) ; Number of LABs  (Total = 2) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 4.50) ; Number of LABs  (Total = 2) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 1                           ;
; 2                                               ; 0                           ;
; 3                                               ; 0                           ;
; 4                                               ; 0                           ;
; 5                                               ; 0                           ;
; 6                                               ; 0                           ;
; 7                                               ; 0                           ;
; 8                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 5.50) ; Number of LABs  (Total = 2) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 0                           ;
; 11                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue May 27 18:15:32 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DDS -c DDS
Info: Selected device EP1C3T144C8 for design "DDS"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EP1C6T144C8 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "CLK" to use Global clock in PIN 93
Info: Automatically promoted signal "RESET" to use Global clock
Info: Pin "RESET" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 2.442 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y1; Fanout = 11; REG Node = 'SUM:U0|TEMP[8]'
    Info: 2: + IC(0.471 ns) + CELL(0.575 ns) = 1.046 ns; Loc. = LAB_X15_Y1; Fanout = 2; COMB Node = 'SUM:U0|TEMP[8]~73COUT1_105'
    Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.126 ns; Loc. = LAB_X15_Y1; Fanout = 2; COMB Node = 'SUM:U0|TEMP[9]~77COUT1_106'
    Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.206 ns; Loc. = LAB_X15_Y1; Fanout = 2; COMB Node = 'SUM:U0|TEMP[10]~81COUT1_107'
    Info: 5: + IC(0.000 ns) + CELL(0.080 ns)