dds.tan.summary

实现DDS频率可调得VHDL程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.968 ns
From           : M[0]
To             : SUM:U0|TEMP[15]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.075 ns
From           : rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg9
To             : Q[4]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -5.673 ns
From           : EN
To             : SUM:U0|TEMP[15]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : SUM:U0|TEMP[9]
To             : SUM:U0|TEMP[13]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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